# US 10,504,835 B1 · Package structure, semiconductor chip and method of fabricating the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,835 B1
- Document ID: US10504835B1
- Status: Granted
- Kind: B1
- Application number: 16/035,710
- Filed: 2018-07-16
- Granted: 2019-12-10
- Earliest claimed: 2018-07-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chuei-Tang Wang; Chung-Hao Tsai; Chen-Hua Yu; Wei-Ting Chen
- Web page: https://patentgrep.com/patent/US10504835B1

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10D 1/68: Capacitors having no potential barriers
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01955: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

## Claims

### Claim 1

A semiconductor chip, comprising:
a die substrate;
a plurality of first bonding structures disposed on the die substrate;
a plurality of conductive elements disposed on the die substrate adjacent to the plurality of first bonding structures;
a first passivation layer encapsulating the plurality of first bonding structures and the plurality of conductive elements, wherein a top surface of the first passivation layer is coplanar with a top surface of the plurality of first bonding structures and a top surface of the plurality of conductive elements;
at least one integrated device disposed on the die substrate over the plurality of first bonding structures, wherein the integrated device comprises a plurality of second bonding structures and a plurality of conductive pillars, and the plurality of second bonding structures is hybrid bonded to the plurality of first bonding structures;
a plurality of conductive posts disposed on the plurality of conductive elements and surrounding the integrated device; and
a protection layer encapsulating the integrated device and the plurality of conductive posts.

### Claim 2 (depends on 1)

The semiconductor chip according to claim 1, wherein the integrated device comprises:
a substrate layer having a first surface and a second surface opposite to the first surface;
a capacitor embedded in the substrate layer;
the plurality of second bonding structures located on the first surface of the substrate layer;
the plurality of conductive pillars located on the second surface of the substrate layer; and
a plurality of through vias located in the substrate layer and electrically connecting the plurality of second bonding structures to the plurality of conductive pillars.

### Claim 3 (depends on 2)

The semiconductor chip according to claim 2, wherein the semiconductor chip further comprises a plurality of first conductive pads disposed on the die substrate adjacent to the plurality of first bonding structures.

### Claim 4 (depends on 3)

The semiconductor chip according to claim 3, wherein the integrated device further comprises a plurality of second conductive pads disposed on the first surface of the substrate layer adjacent to the plurality of second bonding structures, and the plurality of second conductive pads is facing the plurality of first conductive pads.

### Claim 5 (depends on 1)

The semiconductor chip according to claim 1, wherein the semiconductor chip further comprises a plurality of conductive bumps disposed on the plurality of conductive pillars and the plurality of conductive posts.

### Claim 6 (depends on 1)

The semiconductor chip according to claim 1, wherein the integrated device further comprises a second passivation layer encapsulating the second bonding structures, and the second passivation layer is bonded to the first passivation layer.

### Claim 7 (depends on 1)

The semiconductor chip according to claim 1, wherein the semiconductor chip comprises two or more integrated devices disposed on the die substrate over the plurality of first bonding structures.

### Claim 8

A package structure, comprising:
a semiconductor chip, the semiconductor chip comprises:
a die substrate;
a plurality of first bonding structures disposed on the die substrate;
a plurality of conductive elements disposed on the die substrate adjacent to the plurality of first bonding structures;
at least one integrated device disposed on the die substrate over the plurality of first bonding structures, wherein the integrated device comprises a plurality of second bonding structures and a plurality of conductive pillars, and the plurality of second bonding structures is hybrid bonded to the plurality of first bonding structures;
a plurality of conductive posts disposed on the plurality of conductive elements and surrounding the integrated device, wherein a top surface of the plurality of conductive posts is coplanar with a top surface of the plurality of conductive pillars; and
a protection layer encapsulating the integrated device and the plurality of conductive posts;
an insulating encapsulant encapsulating the semiconductor chip;
a redistribution layer disposed on the semiconductor chip and the insulating encapsulant, wherein the redistribution layer is electrically connected to the plurality of conductive pillars of the integrated device and electrically connected the plurality of conductive posts.

### Claim 9 (depends on 8)

The package structure according to claim 8, wherein the semiconductor chip further comprises a plurality of conductive bumps connected to the plurality of conductive pillars and the plurality of conductive posts, and the redistribution layer is electrically connected to the plurality of conductive pillars of the integrated device and electrically connected the plurality of conductive posts through the plurality of conductive bumps.

### Claim 10 (depends on 8)

The package structure according to claim 8, wherein the semiconductor chip further comprises a plurality of first conductive pads disposed on the die substrate adjacent to the plurality of first bonding structures.

### Claim 11 (depends on 10)

The package structure according to claim 10, wherein the integrated device further comprises a plurality of second conductive pads disposed adjacent to the plurality of second bonding structures, and the plurality of second conductive pads is facing the plurality of first conductive pads.

### Claim 12 (depends on 8)

The package structure according to claim 8, wherein in the integrated device, the plurality of second bonding structures is electrically connected to the plurality of conductive pillars.

### Claim 13 (depends on 8)

The package structure according to claim 8, wherein the at least one integrated device is located in between the die substrate and the redistribution layer.

### Claim 14 (depends on 8)

The package structure according to claim 8, wherein the semiconductor chip comprises two or more integrated devices disposed on the die substrate over the plurality of first bonding structures.

### Claim 15 (depends on 8)

The package structure according to claim 8, further comprising a plurality of through insulator vias surrounding the semiconductor chip and encapsulated by the insulating encapsulant, wherein the redistribution layer is electrically connected to the plurality of through insulator vias.

### Claim 16

A method of fabricating a semiconductor chip, comprising:
providing a semiconductor wafer, the semiconductor wafer comprises a die substrate, a plurality of first bonding structures disposed on the die substrate, a plurality of conductive elements disposed on the die substrate adjacent to the plurality of first bonding structures, and a first passivation layer encapsulating the plurality of first bonding structures and the plurality of conductive elements, wherein a top surface of the first passivation layer is coplanar with a top surface of the plurality of first bonding structures and a top surface of the plurality of conductive elements;
providing a plurality of integrated devices, each of the integrated devices comprise a plurality of second bonding structures and a plurality of conductive pillars;
bonding the integrated devices on the semiconductor wafer by joining the plurality of second bonding structures to the plurality of first bonding structures through hybrid bonding;
forming a plurality of conductive posts on the plurality of conductive elements, wherein the plurality of conductive posts surround the integrated devices;
forming a protection layer encapsulating the integrated devices and the plurality of conductive posts; and
performing a dicing process to separate the semiconductor wafer into a plurality of semiconductor chips.

### Claim 17 (depends on 16)

The method of fabricating the semiconductor chip according to claim 16, further comprising forming a seed layer on the plurality of conductive elements after bonding the integrated devices on the semiconductor wafer, and forming the plurality of conductive posts on the seed layer over the plurality of conductive elements.

### Claim 18 (depends on 16)

The method of fabricating the semiconductor chip according to claim 16, further comprises providing a plurality of conductive bumps on the plurality of conductive pillars and the plurality of conductive posts prior to the dicing process.

### Claim 19 (depends on 16)

The method of fabricating the semiconductor chip according to claim 16, wherein each of the integrated devices are formed by the following steps:
providing a substrate layer having a first surface and a second surface opposite to the first surface;
forming a plurality of through vias in the substrate layer;
forming a capacitor in the substrate layer, wherein the capacitor is surrounded by the plurality of through vias;
forming the plurality of second bonding structures on the first surface of the substrate layer, wherein the plurality of second bonding structures is electrically connected to the plurality of through vias; and
forming the plurality of conductive pillars on the second surface of the substrate layer, wherein the plurality of conductive pillars is electrically connected to the plurality of through vias.

### Claim 20 (depends on 19)

The method of fabricating the semiconductor chip according to claim 19, wherein the semiconductor chip is provided with a plurality of first conductive pads disposed on the die substrate adjacent to the plurality of first bonding structures, and the integrated devices are formed with a plurality of second conductive pads disposed on the first surface of the substrate layer, and the plurality of second conductive pads is facing the plurality of first conductive pads after hybrid bonding.