# US 10,504,832 B2 · Method for manufacturing copper layer

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- Number: US 10,504,832 B2
- Document ID: US10504832B2
- Status: Granted
- Kind: B2
- Application number: 14/988,157
- Filed: 2016-01-05
- Published: 2016-05-05
- Granted: 2019-12-10
- Earliest claimed: 2014-05-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Ken-Yu Chang; Hung-Wen Su
- Web page: https://patentgrep.com/patent/US10504832B2

## CPC

- H10W 20/42: Vias, e.g. via plugs
- C23C 14/046: {Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates}
- C23C 14/165: {by cathodic sputtering}
- C23C 14/345: {using substrate bias}
- C23C 14/35: by application of a magnetic field, e.g. magnetron sputtering {(C23C14/3457 takes precedence)}
- H10P 14/44: Physical vapour deposition [PVD]
- H10W 20/033: {in openings in dielectrics}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/043: {for electroplating}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a dielectric over the substrate; forming a trench recessed under a top surface of the dielectric;
forming a barrier layer on a lateral sidewall of the trench; and
depositing a first copper layer over the barrier layer and the top surface of the dielectric, wherein the depositing provides a ratio of the thickness of the first copper layer on the barrier layer at a middle portion of the lateral sidewall and the thickness of the first copper layer over the top surface is greater than 1.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the depositing the first copper layer comprises performing a physical vapor deposition (PVD) by using a Radio Frequency (RF) capacitively coupled plasma (CCP) sputter system, a predetermined resputter ratio, which is a ratio of the thickness of the first copper layer applied to the substrate without a substrate bias to the thickness of first copper layer applied to the substrate with the substrate bias, is controlled so that the ratio of the thickness of the first copper layer on the barrier layer at the lateral sidewall and the thickness of the first copper layer over the top surface is greater than 1.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the Activation (ACT) current in the RF CCP sputter system is about from 5 mA to 50 mA.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising a fill-in operation by depositing a second copper layer in the trench over the first copper layer.

### Claim 5 (depends on 4)

The method according to claim 4, further comprising performing an annealing operation over the first copper layer and prior to the depositing of the second copper layer.

### Claim 6

A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a dielectric over the substrate;
forming an opening recessed under a top surface of the dielectric;
forming a barrier layer on a sidewall of the opening;
performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer; and
reflowing the copper layer by an annealing operation,
wherein a resputter ratio, which is a ratio of the thickness of the copper layer applied to the substrate without a substrate bias to the thickness of copper layer applied to the substrate with the substrate bias, is greater than 2.5.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the performing a physical vapor deposition (PVD) comprises using a direct-current (DC) magnetron sputter system.

### Claim 8 (depends on 7)

The method according to claim 7, wherein an AC (alternate current) bias or DC bias (wafer bias) in the DC magnetron sputter system is greater than 600 W.

### Claim 9 (depends on 6)

The method according to claim 6, wherein the barrier layer is a metallic nitride compound comprises TiN, TaN, WN, MoN, OsN or MnN.

### Claim 10 (depends on 6)

The method according to claim 6, further comprising a fill-in operation which fills the opening with conductive materials.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the fill-in operation comprises performing a PVD operation.

### Claim 12 (depends on 6)

The method according to claim 6, wherein:
a range of a temperature for the annealing operation is around 150-500° C.,
a range of a concentration of Hydrogen gas is around 0% to 100%, and
a range of a time for the annealing operation is around 3-600 seconds.

### Claim 13 (depends on 6)

The method according to claim 6, wherein an impurity concentration of the copper layer is below about 1 ppm.

### Claim 14 (depends on 6)

The method according to claim 6, wherein a critical dimension of the semiconductor structure is less than about 25 nm.

### Claim 15

A method of forming a semiconductor structure, comprising:
forming a substrate;
forming a dielectric over the substrate;
forming a damascene interconnect structure with a critical dimension (CD) less than about 38 nm and surrounded by the dielectric, wherein the damascene interconnect comprises: a barrier layer adjacent to a sidewall of the dielectric and the barrier layer comprising a metallic nitride compound; and
forming a first copper film in a deposition operation with an impurity concentration below about 1 ppm disposed over the barrier layer and the top surface of the dielectric, wherein the deposition operation provides a ratio of a thickness of the first copper film at a middle portion of a lateral sidewall of the dielectric and a thickness of the first copper film over a top surface of the dielectric is greater than 1.

### Claim 16 (depends on 15)

The method of claim 15, wherein the metallic nitride compound comprises TiN, TaN, WN, MoN, OsN, or MnN.

### Claim 17 (depends on 15)

The method of claim 15, further comprising a glue layer over the barrier layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the glue layer comprises Ti, Ta, W, Mo, Co, TiW, Os, or Mn.

### Claim 19 (depends on 15)

The method of claim 15, wherein the CD is less than about 25 nm.

### Claim 20 (depends on 15)

The method of claim 15, further comprising performing a fill-in operation by depositing a second copper film over the first copper film at the lateral sidewall and the top surface of the dielectric.