# US 10,504,831 B2 · Electronic circuit and camera > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,831 B2 - Document ID: US10504831B2 - Status: Granted - Kind: B2 - Application number: 15/916,775 - Filed: 2018-03-09 - Published: 2018-07-12 - Granted: 2019-12-10 - Earliest claimed: 2015-02-27 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Hideo Kobayashi; Kazuo Yamazaki; Hiroki Hiyama - Web page: https://patentgrep.com/patent/US10504831B2 ## CPC - H10W 72/00: Interconnections or connectors in packages - H04N 25/745: {Circuitry for generating timing or clock signals} - H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first group of signals are composed of signals synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second group of signals are composed of signals synchronized with a second edge that is the other of the rising edge and falling edge. The transmission path includes first transmission lines for transmitting the signals composing the first group and second transmission lines for transmitting the signals composing the second group, and the first and second transmission lines are alternately arranged. ## Claims ### Claim 1 An electronic circuit comprising: a first circuit configured to receive a first signal synchronized with a first edge that is one of a rising edge and a falling edge of a clock signal, and to output a second signal synchronized with the first edge; a second circuit configured to receive the second signal and to output a third signal converted from the second signal, the third signal being synchronized with a second edge that is the other of the rising edge and the falling edge; and a third circuit configured to receive the third signal and a fourth signal synchronized with the second edge and to output a fifth signal synchronized with the second edge. ### Claim 2 (depends on 1) The electronic circuit according to claim 1, wherein a cycle of the first signal is larger than a cycle of the fourth signal. ### Claim 3 (depends on 1) The electronic circuit according to claim 1, wherein the second circuit is further configured to receive the clock signal and to generate the third signal in accordance with the second signal and the clock signal. ### Claim 4 (depends on 1) The electronic circuit according to claim 1, wherein the first circuit is further configured to receive a sixth signal synchronized with the first edge and to generate the second signal in accordance with the first signal and the sixth signal. ### Claim 5 (depends on 4) The electronic circuit according to claim 4, further comprising: a signal generator configured to generate the first signal, the fourth signal, and the sixth signal; a first transmission line configured to transmit the first signal from the signal generator to the first circuit; a second transmission line configured to transmit the fourth signal from the signal generator to the third circuit; and a third transmission line configured to transmit the sixth signal from the signal generator to the first circuit, wherein the second transmission line is arranged between the first transmission line and the third transmission line. ### Claim 6 (depends on 4) The electronic circuit according to claim 4, wherein the third circuit is further configured to receive a seventh signal synchronized with the second edge and having a phase different from that of the fourth signal, and wherein the third circuit is further configured to generate the fifth signal in accordance with the third signal, the fourth signal, and the seventh signal. ### Claim 7 (depends on 6) The electronic circuit according to claim 6, further comprising: a signal generator configured to generate the first signal, the fourth signal, the sixth signal, and the seventh signal; a first transmission line configured to transmit the first signal from the signal generator to the first circuit; a second transmission line configured to transmit the fourth signal from the signal generator to the third circuit; and a third transmission line configured to transmit the sixth signal from the signal generator to the first circuit; and a fourth transmission line configured to transmit the seventh signal from the signal generator to the third circuit, wherein the first transmission line is arranged between the third transmission line and the fourth transmission line, and the second transmission line is arranged between the first transmission line and the third transmission line. ### Claim 8 (depends on 1) A solid state image sensor comprising: an electronic circuit according to claim 1; a plurality of pixels arranged to form a plurality of rows and a plurality of columns; and a plurality of memories respectively corresponding to the plurality of columns, wherein the electronic circuit includes a plurality of sets each including the first circuit, the second circuit, and the third circuit, with the plurality of sets respectively corresponding to the plurality of memories, and with the third circuit of each of the plurality of sets being connected to a corresponding memory of the plurality of memories. ### Claim 9 (depends on 1) The electronic circuit according to claim 1, further comprising: a generating circuit having a first output node and a second output node, the first output node configured to output the first signal, the second output node configured to output the fourth signal, the fourth signal having a cycle shorter than a cycle of the first signal; and a transmission path including a first transmission line and a second transmission line, the first transmission line being electrically connected to the first output node, the second transmission line being electrically connected to the second output node, wherein the first circuit is electrically connected to the first transmission line, and wherein the third circuit is electrically connected to the second transmission line. ### Claim 10 (depends on 9) The electronic circuit according to claim 9, wherein the generating circuit includes a logic circuit configured to generate a plurality of bit signals by operating in response to the clock signal and a timing adjusting circuit configured to generate the first signal and the fourth signal in accordance with the plurality of bit signals output from the logic circuit. ### Claim 11 (depends on 10) The electronic circuit according to claim 10, wherein the timing adjusting circuit includes a plurality of first flip flops configured to generate the first signal by performing synchronization in accordance with the first edge and a plurality of second flip flops configured to generate the fourth signal by performing synchronization in accordance with the second edge, and a signal line configured to provide the first edge to the plurality of first flip flops and a signal line configured to provide the second edge to the plurality of second flip flops do not intersect with each other. ### Claim 12 (depends on 11) The electronic circuit according to claim 11, wherein the logic circuit includes a counter configured to perform a count operation in response to the clock signal. ### Claim 13 (depends on 10) The electronic circuit according to claim 10, wherein the logic circuit includes a counter configured to perform a count operation in response to the clock signal. ### Claim 14 (depends on 13) The electronic circuit according to claim 13, wherein the counter comprises a binary counter. ### Claim 15 (depends on 13) The electronic circuit according to claim 13, wherein the counter comprises a Gray code counter. ### Claim 16 (depends on 15) The electronic circuit according to claim 15, wherein the counter has at least one of a function to reset a count value and a function to set a count value. ### Claim 17 (depends on 9) The electronic circuit according to claim 9, wherein the generating circuit generates a first group of signals including the first signal, and a second group of signals including the fourth signal, wherein the first group of signals are synchronized with the first edge, and the second group of signals are synchronized with the second edge, wherein the transmission path includes a plurality of first transmission lines including the first transmission line, each configured to transmit a corresponding one of the first group of signals and a plurality of second transmission lines including the second transmission line, each configured to transmit a corresponding one of the second group of signals, and wherein the plurality of first transmission lines and the plurality of second transmission lines are alternately arranged. ### Claim 18 (depends on 1) A camera comprising: a solid state image sensor including the electronic circuit according to claim 1; and a processor configured to process a signal output from the solid state image sensor.