# US 10,504,828 B2 · Semiconductor package and circuit substrate thereof

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- Number: US 10,504,828 B2
- Document ID: US10504828B2
- Status: Granted
- Kind: B2
- Application number: 15/990,747
- Filed: 2018-05-28
- Published: 2019-09-12
- Granted: 2019-12-10
- Earliest claimed: 2018-03-12
- Assignees: Chipbond Technology Corporation
- Applicants: Chipbond Technology Corporation
- Inventors: Chin-Tang Hsieh
- Web page: https://patentgrep.com/patent/US10504828B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/688: {Flexible insulating substrates}
- H10W 70/69: Insulating materials thereof
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 72/072: {of bump connectors}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

## Claims

### Claim 1

A circuit substrate comprising:
a carrier having a surface;
a plurality of first leads formed on the surface, wherein each of the first leads has a first upper wide portion, a first narrow portion, a first lower wide portion, an internal extending portion and a first lead section which are connected sequentially and wherein the first upper wide portion, the first narrow portion, the first lower wide portion, and the internal extending portion are located in a first bonding area for bonding a chip; and
a plurality of second leads formed on the surface, wherein the first and second leads are aligned alternately along a transverse direction, wherein each of the second leads has an external extending portion, a second upper wide portion, a second narrow portion, a second lower wide portion, and a second lead section which are connected sequentially and wherein the external extending portion, the second upper wide portion, the second narrow portion, and the second lower wide portion are located in a second bonding area for bonding the chip; wherein the first upper wide portion and the first lower wide portion are wider than the first narrow portion and the internal extending portion along the transverse direction such that a first upper notch facing toward the second upper wide portion and a first lower notch facing toward the second lower wide portion are formed in the first bonding area of each of the first leads; wherein the second upper wide portion and the second lower wide portion are wider than the external extending portion and the second narrow portion along the transverse direction such that a second upper notch facing toward the first upper wide portion and a second lower notch facing toward the first lower wide portion are formed in the second bonding area of each of the second leads; wherein the first and second bonding areas are aligned alternately along the transverse direction and flush with each other; wherein the first upper wide portion is located in an end of the first bonding area; wherein the external extending portion is located in an end of the second bonding area; and wherein the first upper wide portion and the external extending portion are flush with each other, wherein a first pitch is defined between the first narrow portion and the second upper wide portion, and a second pitch is defined between the second narrow portion and the first lower wide portion, wherein the first pitch is substantially equal to the second pitch, and wherein the first upper wide portion and the first lower wide portion have substantially identical width, and the first narrow portion and the internal extending portion have substantially identical width.

### Claim 2 (depends on 1)

The circuit substrate in accordance with claim 1, wherein the first and second pitches are less than or equal to 20 μm.

### Claim 3 (depends on 1)

The circuit substrate in accordance with claim 1, wherein an edge of the first upper wide portion protrudes from an edge of the first narrow portion approximately 0.5 to 3.5 μm.

### Claim 4 (depends on 1)

The circuit substrate in accordance with claim 1, wherein the first upper wide portion has a width and a thickness, and the width is not less than the thickness.

### Claim 5 (depends on 1)

The circuit substrate in accordance with claim 1, wherein the first narrow portion has a width and a thickness, and the width is less than the thickness.

### Claim 6

A semiconductor package comprising:
a chip including a plurality of first bumps and a plurality of second bumps; and
a circuit substrate including a carrier, a plurality of first leads, and a plurality of second leads, the first and second leads are formed on a surface of the carrier and aligned alternately along a transverse direction, each of the first leads has a first upper wide portion, a first narrow portion, a first lower wide portion, an internal extending portion, and a first lead section which are connected sequentially, wherein the first upper wide portion, the first narrow portion, the first lower wide portion, and the internal extending portion are located in a first bonding area and bonded with the first bump, each of the second leads has an external extending portion, a second upper wide portion, a second narrow portion, a second lower wide portion, and a second lead section which are connected sequentially, wherein the external extending portion, the second upper wide portion, the second narrow portion, and the second lower wide portion are located in a second bonding area and bonded with the second bump;
wherein the first upper wide portion and the first lower wide portion are wider than the first narrow portion and the internal extending portion along the transverse direction such that a first upper notch facing toward the second upper wide portion and a first lower notch facing toward the second lower wide portion are formed in the first bonding area of each of the first leads;
wherein the second upper wide portion and the second lower wide portion are wider than the external extending portion and the second narrow portion along the transverse direction such that a second upper notch facing toward the first upper wide portion and a second lower notch facing toward the first lower wide portion are formed in the second bonding area of each of the second leads; wherein the first and second bonding areas are aligned alternately along the transverse direction and flush with each other; wherein the first upper wide portion is located on an end of the first bonding area; wherein the external extending portion is located on an end of the second bonding area; and wherein the first upper wide portion and the external extending portion are flush with each other, wherein a first pitch is defined between the first narrow portion and the second upper wide portion, and a second pitch is defined between the second narrow portion and the first lower wide portion, wherein the first pitch is substantially equal to the second pitch, and wherein the first upper wide portion and the first lower wide portion have substantially identical width, and the first narrow portion and the internal extending portion have substantially identical width.

### Claim 7 (depends on 6)

The semiconductor package in accordance with claim 6, wherein the first and second pitches are less than or equal to 20 μm.

### Claim 8 (depends on 6)

The semiconductor package in accordance with claim 6, wherein an edge of the first upper wide portion protrudes from an edge of the first narrow portion approximately 0.5 to 3.5 μm.

### Claim 9 (depends on 6)

The semiconductor package in accordance with claim 6, wherein the first upper wide portion has a width and a thickness, and the width is not less than the thickness.

### Claim 10 (depends on 6)

The semiconductor package in accordance with claim 6, wherein the first narrow portion has a width and a thickness, and the width is less than the thickness.

### Claim 11 (depends on 6)

The semiconductor package in accordance with claim 6, wherein the first bumps, the first upper wide portions and the first lower wide portions have substantially identical width.