# US 10,504,825 B2 · Fan-out semiconductor package

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- Number: US 10,504,825 B2
- Document ID: US10504825B2
- Status: Granted
- Kind: B2
- Application number: 15/988,541
- Filed: 2018-05-24
- Published: 2019-05-09
- Granted: 2019-12-10
- Earliest claimed: 2017-11-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jeong Il Lee; Jeong Ho Lee; Jin Su Kim; Bong Ju Cho
- Web page: https://patentgrep.com/patent/US10504825B2

## CPC

- H10W 70/685: comprising multiple insulating layers
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/69: Insulating materials thereof
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/655: Fan-out layouts
- H10W 70/656: Fan-in layouts
- H10W 70/68: Shapes or dispositions thereof
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/07253: {changes in shapes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps.

## Claims

### Claim 1

A fan-out semiconductor package comprising:
a frame including
a plurality of insulating layers,
a plurality of wiring layers disposed on the plurality of insulating layers, and
a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and the frame having a recess portion having a bottom layer disposed on a bottom surface thereof;
a semiconductor chip having
connection pads,
an active surface on which the connection pads are disposed, and
an inactive surface opposing the active surface, and being disposed in the recess portion so that the inactive surface faces the bottom layer;
first metal bumps disposed on the connection pads of the semiconductor chip;
second metal bumps disposed on an uppermost wiring layer of the plurality of wiring layers;
an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion, wherein an upper surface of the encapsulant is coplanar with upper surfaces of each of the first and second metal bumps; and
a connection member including an insulating layer disposed on the coplanar upper surfaces of the encapsulant and first and second metal bumps to face the frame and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, and first and second connection vias penetrating through the insulating layer and integrated with the redistribution layer, the redistribution layer connected to the first and second metal bumps through the first and second connection vias, respectively.

### Claim 2 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the first and second metal bumps are copper (Cu) posts.

### Claim 3 (depends on 2)

The fan-out semiconductor package of claim 2, wherein each of the first and second metal bumps has a rectangular cross-sectional shape.

### Claim 4 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and
the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.

### Claim 5 (depends on 4)

The fan-out semiconductor package of claim 4, wherein the number of first build-up insulating layers and the number of second build-up insulating layers are the same as each other.

### Claim 6 (depends on 4)

The fan-out semiconductor package of claim 4, wherein the recess portion penetrates through at least the core insulating layer and penetrates through at least one of the one or more first and second build-up insulating layers.

### Claim 7 (depends on 1)

The fan-out semiconductor package of claim 1, wherein a region of the bottom layer exposed by the recess portion has a thickness smaller than that of an edge region of the bottom layer that is not exposed.

### Claim 8 (depends on 4)

The fan-out semiconductor package of claim 4, wherein first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer are tapered in opposite directions to each other.

### Claim 9 (depends on 1)

The fan-out semiconductor package of claim 1, wherein walls of the recess portion are tapered.

### Claim 10 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the inactive surface of the semiconductor chip is attached to the bottom layer through an adhesive member.

### Claim 11 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the bottom layer is a metal layer,
at least one of the plurality of wiring layers includes a ground, and
the metal layer is electrically connected to the ground.

### Claim 12 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the bottom layer has a planar area greater than that of the inactive surface of the semiconductor chip.

### Claim 13 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip.

### Claim 14 (depends on 1)

The fan-out semiconductor package of claim 1, further comprising:
a first passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer;
underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed redistribution layer; and
electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.

### Claim 15 (depends on 14)

The fan-out semiconductor package of claim 14, further comprising a second passivation layer disposed beneath the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.

### Claim 16 (depends on 1)

The fan-out semiconductor package of claim 1, wherein at least one of the wiring layers are disposed on a level below the bottom layer.

### Claim 17

A fan-out semiconductor package, comprising:
a frame having a recess having a bottom layer disposed on a bottom surface of the recess, and having wiring layers disposed on each of an upper and a lower surface of the frame;
a semiconductor chip having an active surface and an inactive surface and being disposed in the recess such that the inactive surface contacts the bottom layer, the active surface comprising connection pads;
first metal bumps disposed on the connection pads of the semiconductor chip;
second metal bumps disposed on an uppermost wiring layer disposed on the frame;
an encapsulant covering at least portions of the frame, the semiconductor chip, the first metal bumps and the second metal bumps and filling at least a portion of the recess, wherein an upper surface of the encapsulant is coplanar with upper surfaces of each of the first and second metal bumps; and
a connection member including an insulating layer disposed on the coplanar upper surfaces of the encapsulant and first and second metal bumps to face the frame and the active surface of the semiconductor chip, a redistribution layer disposed on the insulating layer, and first and second connection vias penetrating through the insulating layer and integrated with the redistribution layer, the redistribution layer connected to the first and second metal bumps through the first and second connection vias, respectively.

### Claim 18 (depends on 17)

The fan-out semiconductor package of claim 17, wherein each of the first and second metal bumps has a rectangular cross-sectional shape.