# US 10,504,822 B2 · Semiconductor device

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- Number: US 10,504,822 B2
- Document ID: US10504822B2
- Status: Granted
- Kind: B2
- Application number: 15/868,798
- Filed: 2018-01-11
- Published: 2018-05-10
- Granted: 2019-12-10
- Earliest claimed: 2011-10-31
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Shoji Yasunaga; Mamoru Yamagami
- Web page: https://patentgrep.com/patent/US10504822B2

## CPC

- H10W 70/461: {specially adapted for cooling}
- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 40/778: {in encapsulations}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/427: {Bent parts}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 72/072: {of bump connectors}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/07521: {Aligning}
- H10W 72/07554: {changes in dispositions}
- H10W 72/07555: {changes in materials}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/261: {Functions other than electrical connecting}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/551: {Materials of bond wires}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/957: {Multiple bond pads having different materials}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

[Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

## Claims

### Claim 1

A semiconductor device comprising:
a die pad having a main surface and a rear surface facing in opposite directions;
a semiconductor chip mounted on the main surface of the die pad and having one or more electrodes;
a wire; and
a sealing resin portion covering the die pad and the semiconductor chip;
wherein the die pad is formed with a pair of press marks spaced from each other, and
the wire has an end bonded to a place on the electrode between the pair of press marks within a direction in which the pair of press marks are spaced from each other.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the end of the wire is bonded to cross a straight line which connects the pair of press marks with each other, on the electrode.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising a wire bonding portion spaced from the die pad,
wherein the wire bonding portion is formed with an additional pair of press marks which are spaced from each other, and
the wire has another end bonded to a place on the wire bonding portion between the additional pair of press marks within a direction in which the additional pair of press marks are spaced from each other.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein said another end of the wire is bonded across a straight line which connects the additional pair of press marks with each other on the wire bonding portion.

### Claim 5

A semiconductor device comprising:
a die pad including a main surface and a rear surface facing in opposite directions;
a semiconductor chip mounted on the main surface of the die pad and including one or more electrodes;
leads electrically connected to the semiconductor chip via respective wires; and
a sealing resin portion covering the die pad, the semiconductor chip and part of the leads;
wherein one of the leads is formed with a pair of press marks on its surface to sandwich a bonding place where a corresponding one of the wires connected to said one of the leads has its end bonded.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein said one of the leads formed with the press marks has a wider region than another of the leads not formed with the press marks.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the wires comprise wires of different thicknesses, and
said corresponding one of the wires is a wire of a greater thickness.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, comprising a plurality of semiconductor chips,
wherein the wire of the greater thickness is used only for electrical connection between one of the semiconductor chips and one of the leads.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein the main surface of the die pad is formed with the pair of press marks spaced from each other so as to sandwich the semiconductor chip.

### Claim 10 (depends on 5)

The semiconductor device according to claim 5, comprising a plurality of semiconductor chips including an output transistor and a controlling semiconductor chip therefor,
wherein the output transistor is bonded to one of the leads that is formed with the press marks spaced from each other to sandwich the output transistor.