# US 10,504,819 B2 · Integrated circuit package with enhanced cooling structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,819 B2 - Document ID: US10504819B2 - Status: Granted - Kind: B2 - Application number: 14/938,486 - Filed: 2015-11-11 - Published: 2017-05-11 - Granted: 2019-12-10 - Earliest claimed: 2015-11-11 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Ravi Gutala; Arifur Rahman; Karthik Chandrasekar - Web page: https://patentgrep.com/patent/US10504819B2 ## CPC - H10W 40/47: by flowing liquids, e.g. forced water cooling - G01K 7/343: {the dielectric constant of which is temperature dependant} - G01N 25/00: Investigating or analyzing materials by the use of thermal means (G01N3/00 - G01N23/00 take precedence) - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/43: by flowing gases, e.g. forced air cooling - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 90/00: Package configurations - H10W 40/037: {Assembling together parts thereof} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/30: wherein the packaged device is completely immersed in a fluid other than air, e.g. immersed in a cryogenic fluid - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) ## Abstract An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second sub-channels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region. ## Claims ### Claim 1 An integrated circuit package comprising: a single integrated circuit die comprising first and second circuit regions and a surface; a cooling structure on the surface of the integrated circuit die, wherein the cooling structure comprises a plurality of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant, and wherein the cooling channel comprises: a first sub-channel having a first size between a first subset of the micropipe interconnects for cooling the first circuit region using the coolant; and a second sub-channel having a second size between a second subset of the micropipe interconnects for cooling the second circuit region using the coolant, wherein the second size is different than the first size; an inlet port connected to the cooling structure for admitting the coolant to pass through the first and second sub-channels in the cooling channel of the cooling structure, wherein the inlet port is positioned next to the first circuit region; and an outlet port connected to the cooling structure for expelling the coolant out of the first and second sub-channels in the cooling channel of the cooling structure, wherein the outlet port is positioned next to the second circuit region, wherein the first circuit region of the integrated circuit die generates a higher heat density than the second circuit region of the integrated circuit die when the integrated circuit die is operating, wherein the micropipe interconnects in the first subset each have a first diameter, and wherein the micropipe interconnects in the second subset each have a second diameter that is different than the first diameter such that the first subset of the micropipe interconnects permit the flow of coolant at a higher volume to cool the first circuit region than the flow of coolant permitted by the second subset of the micropipe interconnects to the second circuit region. ### Claim 2 (depends on 1) The integrated circuit package defined in claim 1, wherein the first size of the first sub-channel is larger than the second size of the second sub-channel. ### Claim 3 (depends on 2) The integrated circuit package defined in claim 2, wherein the cooling structure comprises a monolithically integrated heat sink. ### Claim 4 (depends on 3) The integrated circuit package defined in claim 3, wherein the first circuit region comprises a processor circuit. ### Claim 5 (depends on 4) The integrated circuit package defined in claim 4, wherein the second circuit region comprises a logic array circuit. ### Claim 6 (depends on 3) The integrated circuit package defined in claim 3, wherein the cooling structure further comprises: a substrate adapted to allow the flow of the coolant through the first and second sub-channels in the cooling channel. ### Claim 7 (depends on 6) The integrated circuit package defined in claim 6, wherein the coolant comprises water. ### Claim 8 (depends on 2) The integrated circuit package defined in claim 2, wherein the first circuit region has an uncooled operating temperature that is higher than that of the second circuit region. ### Claim 9 (depends on 8) The integrated circuit package defined in claim 8, further comprising: an additional integrated circuit die. ### Claim 10 (depends on 9) The integrated circuit package defined in claim 9, wherein the coolant is selected from a group consisting of gas and liquid. ### Claim 11 (depends on 1) The integrated circuit package defined in claim 1, wherein each of the micropipe interconnects comprises conductors that connect to through-silicon-vias in the integrated circuit die. ### Claim 12 (depends on 1) The integrated circuit package defined in claim 1, wherein each of the micropipe interconnects in each of the first and second subsets comprises a micropin-fin that comprises at least two vias that extend between a top surface and a bottom surface of the micropin-fin and that connect to the integrated circuit die. ### Claim 13 (depends on 1) The integrated circuit package defined in claim 1, wherein the integrated circuit die comprises a field programmable gate array. ### Claim 14 An integrated circuit package comprising: a single integrated circuit die comprising first and second circuit regions; and a cooling structure on a surface of the integrated circuit die, wherein the cooling structure comprises micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant, and wherein the cooling channel comprises: a first sub-channel between a first subset of the micropipe interconnects for cooling the first circuit region using the coolant; and a second sub-channel between a second subset of the micropipe interconnects for cooling the second circuit region using the coolant; an inlet port connected to the cooling structure for admitting the coolant to pass through the first and second sub-channels in the cooling channel of the cooling structure, wherein the inlet port is positioned next to the first circuit region; and an outlet port connected to the cooling structure for expelling the coolant out of the first and second sub-channels in the cooling channel of the cooling structure, wherein the outlet port is positioned next to the second circuit region, wherein the first circuit region of the integrated circuit die generates a higher heat density than the second circuit region of the integrated circuit die when the integrated circuit die is operating, wherein the micropipe interconnects in the first subset each have a first diameter, and wherein the micropipe interconnects in the second subset each have a second diameter that is different than the first diameter such that the first subset of the micropipe interconnects permit the flow of coolant at a higher volume to cool the first circuit region than the flow of coolant permitted by the second subset of the micropipe interconnects to the second circuit region. ### Claim 15 (depends on 14) The integrated circuit package defined in claim 14, wherein the cooling structure comprises a monolithically integrated heat sink. ### Claim 16 (depends on 14) The integrated circuit package defined in claim 14, wherein the first circuit region has an uncooled operating temperature that is higher than that of the second circuit region. ### Claim 17 (depends on 14) The integrated circuit package defined in claim 14, wherein the cooling structure further comprises: a substrate adapted to allow the flow of the coolant through the first and second sub-channels in the cooling channel. ### Claim 18 (depends on 14) The integrated circuit package defined in claim 14, wherein each of the micropipe interconnects comprises multiple conductors that connect to through-silicon-vias in the integrated circuit die. ### Claim 19 (depends on 14) The integrated circuit package defined in claim 14, wherein each of the micropipe interconnects in each of the first and second subsets comprises a micropin-fin that comprises at least two vias that extend between a top surface and a bottom surface of the micropin-fin and that connect to the integrated circuit die. ### Claim 20 (depends on 14) The integrated circuit package defined in claim 14, wherein the integrated circuit die comprises a field programmable gate array.