# US 10,504,810 B2 · Polymer-based-semiconductor structure with cavity

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- Number: US 10,504,810 B2
- Document ID: US10504810B2
- Status: Granted
- Kind: B2
- Application number: 15/958,812
- Filed: 2018-04-20
- Published: 2018-08-23
- Granted: 2019-12-10
- Earliest claimed: 2015-11-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Hung-Yi Kuo; Hao-Yi Tsai
- Web page: https://patentgrep.com/patent/US10504810B2

## CPC

- H10W 74/124: {the encapsulations having cavities other than that occupied by chips}
- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10D 1/20: Inductors
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A structure includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die, and a cavity in the encapsulating material. The cavity penetrates through the encapsulating material.

## Claims

### Claim 1

A method comprising:
encapsulating a device die in an encapsulating material;
planarizing a top surface of the device die with a top surface of the encapsulating material;
forming at least one dielectric layer over the encapsulating material and the device die;
forming a plurality of redistribution lines in the at least one dielectric layer, wherein the plurality of redistribution lines is electrically coupled to the device die; and
removing a portion of the encapsulating material and the at least one dielectric layer to form a cavity penetrating through the at least one dielectric layer and the encapsulating material.

### Claim 2 (depends on 1)

The method of claim 1 further comprising inserting a component into the cavity.

### Claim 3 (depends on 2)

The method of claim 2, wherein the inserting the component comprises inserting a camera.

### Claim 4 (depends on 2)

The method of claim 2, wherein the inserting the component comprises inserting a ferrite material.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
forming an inductor with a portion coplanar with the device die, wherein the cavity is formed in a region encircled by the inductor, and after the planarizing, a top surface of the portion of the inductor is revealed.

### Claim 6 (depends on 1)

The method of claim 1, wherein the forming the cavity comprises a drilling process selected from drilling using a drill bit, a laser drilling, and a blade cutting.

### Claim 7 (depends on 1)

The method of claim 1, wherein the device die and the encapsulating material are parts of a package, and the method further comprises bonding a package component to the package, wherein the package component covers the cavity.

### Claim 8

A method comprising:
forming a dielectric buffer layer over a carrier;
plating a coil over the dielectric buffer layer;
placing a device die over the dielectric buffer layer;
encapsulating the coil and the device die in an encapsulating material;
forming a redistribution line connecting the coil to the device die; and
forming a through-opening penetrating through the encapsulating material, wherein the forming the through-opening comprises removing a portion of the encapsulating material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the portion of the encapsulating material is encircled by the coil.

### Claim 10 (depends on 8)

The method of claim 8 further comprising:
forming at least one dielectric layer over the encapsulating material, wherein the redistribution line is formed in the at least one dielectric layer; and
removing a portion of the dielectric layer so that the through-opening further extends into the dielectric layer.

### Claim 11 (depends on 8)

The method of claim 8, wherein the through-opening is formed through drilling using a drill bit.

### Claim 12 (depends on 8)

The method of claim 8, wherein the through-opening is formed through laser drill.

### Claim 13 (depends on 8)

The method of claim 8 further comprises inserting a pre-formed discrete component into the through-opening, wherein the pre-formed discrete component is formed before being inserted into the through-opening.

### Claim 14 (depends on 13)

The method of claim 13, wherein the inserting the pre-formed discrete component comprises inserting a camera or a ferrite material.

### Claim 15 (depends on 8)

The method of claim 8 further comprising bonding a package component over the redistribution line, wherein the package component is electrically coupled to one of the coil and the device die through the redistribution line.

### Claim 16

A method comprising:
forming a dielectric buffer layer over a carrier;
forming a coil over the dielectric buffer layer;
encapsulating the coil in an encapsulating material;
forming a plurality of dielectric layers over the coil and the encapsulating material;
demounting the dielectric buffer layer, the coil, and the encapsulating material from the carrier to form a package;
forming an opening in the package, wherein the opening extends into the plurality of dielectric layers and the encapsulating material; and
inserting a discrete device into the opening.

### Claim 17 (depends on 16)

The method of claim 16, wherein the opening is formed by removing portions of the plurality of dielectric layers and the encapsulating material in a common process.

### Claim 18 (depends on 16)

The method of claim 16, wherein the discrete device comprises a first portion at a same level as the encapsulating material, and a second portion level with one of the plurality of dielectric layers.

### Claim 19 (depends on 16)

The method of claim 16 further comprising bonding a package component to the package, wherein the package component overlaps the discrete device.

### Claim 20 (depends on 16)

The method of claim 16, wherein the discrete device is encircled by the coil.