# US 10,504,806 B2 · Semiconductor package with electrical test pads

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- Number: US 10,504,806 B2
- Document ID: US10504806B2
- Status: Granted
- Kind: B2
- Application number: 15/148,754
- Filed: 2016-05-06
- Published: 2017-11-09
- Granted: 2019-12-10
- Earliest claimed: 2016-05-06
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics S.R.L.
- Inventors: Federico Giovanni Ziglioli
- Web page: https://patentgrep.com/patent/US10504806B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 72/0198: {batch processes}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads. In one embodiment, all of the test pads are located on a single surface of the packaging material of the package, which may allow for ease of electrical testing of the package.

## Claims

### Claim 1

A semiconductor package comprising:
a semiconductor die;
a plurality of leads, the semiconductor die electrically coupled to the plurality of leads;
a packaging material around the semiconductor die and first portions of the plurality of leads, second portions of the plurality of leads extending from side surfaces of the packaging material;
a plurality of test pads of conductive ink located directly on an outer exposed surface of the packaging material; and
a plurality of traces of conductive ink having first ends on the second portions of the plurality of leads and second ends coupled to the plurality of test pads, portions of the plurality of traces being located directly on the packaging material.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of test pads are located on a planar surface of the packaging material.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of traces are located on two surfaces of the packaging material.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the two surfaces of the packaging material are at an acute or right angle of each other.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of traces have widths that are less than widths of the plurality of leads.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein:
the packaging material is molding compound;
the plurality of test pads are located on a first planar surface of the molding compound; and
each of the plurality of traces are located on the first planar surface of the molding compound and on a second planar surface of the molding compound.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, further comprising a die pad, the semiconductor die mounted to the die pad.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of test pads and the plurality of traces have thicknesses that are between 1.5 microns to 4 microns.

### Claim 9

A semiconductor package comprising:
a semiconductor die;
a die pad, the semiconductor die mounted to the die pad;
a plurality of leads, the semiconductor die electrically coupled to the plurality of leads;
encapsulation material around the semiconductor die and first portions of the plurality of leads, second portions of the plurality of leads extending from side surfaces of the encapsulation material;
a plurality of test pads of conductive ink located directly on an upper surface of the encapsulation material; and
a plurality of traces of conductive ink coupling the second portions of the plurality of leads to the plurality of test pads, the plurality of traces being directly on second portions of the plurality of leads, side surfaces of the encapsulation material, and on an upper surface of the encapsulation material.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the plurality of test pads are located on a planar surface of the encapsulation material.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, wherein the plurality of test pads have a different pitch from the plurality of leads.