# US 10,504,799 B2 · Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap

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- Number: US 10,504,799 B2
- Document ID: US10504799B2
- Status: Granted
- Kind: B2
- Application number: 15/649,122
- Filed: 2017-07-13
- Published: 2017-11-02
- Granted: 2019-12-10
- Earliest claimed: 2016-02-24
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Takashi Ando; Martin M. Frank; Renee T. Mo; Vijay Narayanan
- Web page: https://patentgrep.com/patent/US10504799B2

## CPC

- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/82: Heterojunctions
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/05: using Group III-V technology
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

## Claims

### Claim 1

A method for forming a plurality of semiconductor devices, comprising:
forming first source and drain regions by implanting a region of a continuous semiconductor substrate formed from a first group IV semiconductor material to define a first channel region in the continuous semiconductor substrate between the first source and drain regions;
forming a region of a second semiconductor material embedded in the continuous semiconductor substrate, comprising second source and drain regions and a second channel region between the second source and drain regions, the second channel region being formed from a group III-V semiconductor material that is different from a semiconductor material of the first channel region by forming a trench in the continuous semiconductor substrate and epitaxially growing the group III-V semiconductor material in the trench;
forming a mask on the continuous semiconductor substrate, wherein the mask has an opening aligned with each of the first channel region and the second channel region;
forming a silicon cap within the openings on each of the first channel region and the second channel region by gas cluster ion beam deposition;
forming a hafnium dioxide gate dielectric layer covering the silicon caps;
activating the hafnium dioxide gate dielectric layer using ozone;
forming a nitrogen-containing layer on the hafnium dioxide gate dielectric layer;
forming an aluminum oxide layer on the nitrogen-containing layer; and
forming a gate metal on the aluminum oxide layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first channel region is coplanar with the second channel region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the openings in the mask layer are formed by etching.

### Claim 4 (depends on 1)

The method of claim 1, further comprising etching away the mask layer after forming the gate.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the nitrogen-containing layer comprises performing one process selected from the group consisting of an ammonia anneal and exposure to a nitrogen plasma.

### Claim 6

A method for forming a plurality of semiconductor devices, comprising:
forming first source and drain regions by implanting a region of a continuous semiconductor substrate formed from a group IV semiconductor material to define a first channel region in the continuous semiconductor substrate between the first source and drain regions;
forming a region of second semiconductor material embedded in the continuous semiconductor substrate, comprising second source and drain regions and a second channel region between the second source and drain regions, wherein the second channel region is coplanar with the first channel region by forming a trench in the continuous semiconductor substrate and epitaxially growing a group III-V semiconductor material in the trench;
forming a mask on the continuous semiconductor substrate, wherein the mask has an opening aligned with each of the first channel region and the second channel region;
forming a silicon cap within the openings on each of the first channel region and the second channel region by gas cluster ion beam deposition;
forming a hafnium dioxide gate dielectric layer over the silicon caps;
activating the hafnium dioxide gate dielectric layer using ozone;
forming a nitrogen-containing layer on the hafnium dioxide gate dielectric layer;
forming an aluminum oxide layer on the nitrogen-containing layer; and
forming a gate metal on the aluminum oxide layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the openings in the mask layer are formed by etching.

### Claim 8 (depends on 7)

The method of claim 7, further comprising etching away the mask layer after forming the gate.

### Claim 9 (depends on 6)

The method of claim 6, wherein forming the nitrogen-containing layer comprises performing one process selected from the group consisting of an ammonia anneal and exposure to a nitrogen plasma.

### Claim 10

A method for forming a plurality of semiconductor devices, comprising:
forming first source and drain regions by implanting a region of a continuous semiconductor substrate formed from a group IV semiconductor material to define a first channel region in the continuous semiconductor substrate between the first source and drain regions;
forming a region of second semiconductor material embedded in the continuous semiconductor substrate, comprising second source and drain regions and a second channel region between the second source and drain regions, wherein the second channel region is coplanar with the first channel region by forming a trench in the continuous semiconductor substrate and epitaxially growing a group III-V semiconductor material in the trench;
depositing a mask layer over the continuous semiconductor substrate with openings directly over the first and second channel regions;
forming a silicon cap on each of the first channel region and the second channel region within the openings of the mask layer by gas cluster ion beam deposition;
forming a hafnium dioxide gate dielectric layer over the silicon caps;
activating the hafnium dioxide gate dielectric layer using ozone;
forming a nitrogen-containing layer on the hafnium dioxide gate dielectric layer;
forming an aluminum oxide layer on the nitrogen containing layer;
forming a gate metal on the aluminum oxide layer; and
etching away the mask layer after forming the gate metal.