# US 10,504,796 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 10,504,796 B2
- Document ID: US10504796B2
- Status: Granted
- Kind: B2
- Application number: 16/234,916
- Filed: 2018-12-28
- Published: 2019-05-09
- Granted: 2019-12-10
- Earliest claimed: 2017-03-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: I-Sheng Chen; Tzu-Chiang Chen; Cheng-Hsien Wu; Chih-Chieh Yeh; Chih-Sheng Chang
- Web page: https://patentgrep.com/patent/US10504796B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/3462: {Nanowires}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and a metal gate. The first gate dielectric layer is around the n-channel. The first dielectric sheath layer is around the first gate dielectric layer. The second gate dielectric layer is around the p-channel. The second dielectric sheath layer is around the second gate dielectric layer, in which the first dielectric sheath layer and the second dielectric sheath layer comprise different materials. The metal gate electrode is around the first dielectric sheath layer and the second dielectric sheath layer.

## Claims

### Claim 1

A semiconductor device, comprising:
an n-channel;
a p-channel;
a first gate dielectric layer around the n-channel;
a first dielectric sheath layer around the first gate dielectric layer;
a second gate dielectric layer around the p-channel;
a second dielectric sheath layer around the second gate dielectric layer, wherein the first dielectric sheath layer and the second dielectric sheath layer comprise different materials; and
a metal gate electrode around the first dielectric sheath layer and the second dielectric sheath layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first gate dielectric layer and the second gate dielectric layer are made of the same high-k dielectric material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric sheath layer comprises yttrium oxide (Y2O3), lutetium(III) oxide (Lu2O3), lanthanum oxide (La2O3), strontium oxide (SrO), erbium (Er), scandium (Sc), or combinations thereof.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric sheath layer comprises aluminum oxide (Al2O3), titanium oxide (TiO2), zirconium oxide (ZrO2), magnesium oxide (MgO), or combinations thereof.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the metal gate electrode continuously extends across the n-channel and the p-channel.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the metal gate electrode is in contact with the first dielectric sheath layer and the second dielectric sheath layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the metal gate electrode has a first portion in contact with the first dielectric sheath layer and a second portion in contact with the second dielectric sheath layer, and the first portion and the second portion of the metal gate electrode are made of the same material.

### Claim 8

A semiconductor device, comprising:
a first channel;
a second channel;
a first dielectric sheath layer around the first channel;
a second dielectric sheath layer around the second channel, wherein the first dielectric sheath layer and the second dielectric sheath layer comprise different materials; and
a metal gate electrode continuously extending across the first dielectric sheath layer and the second dielectric sheath layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a first source/drain structure adjoining the first channel;
a second source/drain structure adjoining the second channel; and
an inter-layer dielectric (ILD) layer interposed between the first source/drain structure and the second source/drain structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a first contact over the first source/drain structure; and
a second contact over the second source/drain structure, wherein the ILD layer is further interposed between the first contact and the second contact.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first source/drain structure comprises an n-type dopant, and the second source/drain structure comprises a p-type dopant.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein a portion of the first dielectric sheath layer is under a bottom surface of the metal gate electrode.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further comprising:
a first gate dielectric layer between the first dielectric sheath layer and the first channel; and
a second gate dielectric layer between the second dielectric sheath layer and the second channel, wherein the first gate dielectric layer and the second gate dielectric layer are made of the same high-k dielectric material.

### Claim 14

A method, comprising:
forming a first nanowire and a second nanowire over a semiconductor substrate;
depositing a first dielectric sheath layer over the first nanowire and the second nanowire;
removing a first portion of the first dielectric sheath layer from the second nanowire, wherein a second portion of the first dielectric sheath layer remains over the first nanowire;
depositing a second dielectric sheath layer over the second nanowire, wherein the first dielectric sheath layer and the second dielectric sheath layer comprise different materials; and
depositing a metal layer over the first dielectric sheath layer and the second dielectric sheath layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein depositing the metal layer is performed such that the metal layer is over and in contact with the first dielectric sheath layer and the second dielectric sheath layer.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
polishing the metal layer, such that a top surface of the polished metal layer is substantially flat.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the first nanowire and the second nanowire comprises forming a third nanowire over the first nanowire; and
wherein depositing the first dielectric sheath layer is performed such that the first dielectric sheath layer has the second portion around the first nanowire and a third portion around the third nanowire and such that the second portion and the third portion of the first dielectric sheath layer are merged together.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the first nanowire and the second nanowire comprises forming a third nanowire over the first nanowire; and
wherein depositing the first dielectric sheath layer is performed such that the first dielectric sheath layer has the second portion around the first nanowire and a third portion around the third nanowire and such that the second portion of the first dielectric sheath layer is spaced from the third portion of the first dielectric sheath layer.

### Claim 19 (depends on 14)

The method of claim 14, wherein forming the first nanowire and the second nanowire comprises forming a third nanowire over the second nanowire; and
wherein depositing the second dielectric sheath layer is performed such that the second dielectric sheath layer has a first portion around the second nanowire and a second portion around the third nanowire and such that the first portion and the second portion of the second dielectric sheath layer are merged together.

### Claim 20 (depends on 14)

The method of claim 14, wherein forming the first nanowire and the second nanowire comprises forming a third nanowire over the second nanowire; and
wherein depositing the second dielectric sheath layer is performed such that the second dielectric sheath layer has a first portion around the second nanowire and a second portion around the third nanowire and such that the first portion of the second dielectric sheath layer is spaced from the second portion of the second dielectric sheath layer.