# US 10,504,795 B2 · Method for patterning a lanthanum containing layer

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- Number: US 10,504,795 B2
- Document ID: US10504795B2
- Status: Granted
- Kind: B2
- Application number: 15/937,472
- Filed: 2018-03-27
- Published: 2019-10-03
- Granted: 2019-12-10
- Earliest claimed: 2018-03-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kun-Yu Lee; Huicheng Chang; Che-Hao Chang; Ching-Hwanq Su; Weng Chang; Xiong-Fei Yu
- Web page: https://patentgrep.com/patent/US10504795B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/6518: {by introduction of substances into an already-existing insulating layer}
- H10P 50/667: {by liquid etching only}
- H10P 50/73: {using masks for insulating materials}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10P 32/20: Diffusion for doping of insulating layers
- H10P 50/283: {by chemical means}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

## Claims

### Claim 1

A method for semiconductor processing, the method comprising:
forming an interfacial layer on a semiconductor material;
forming a high-k dielectric layer over the interfacial layer, the high-k dielectric layer extending over the interfacial layer and along sidewalls of a recess in a dielectric layer, the interfacial layer comprising a different material than the high-k dielectric layer;
forming a film stack over the high-k dielectric layer, wherein the film stack includes a lanthanum containing layer formed over the high-k dielectric layer, a blocking layer formed over the lanthanum containing layer, and a hard mask layer formed over the blocking layer, wherein the blocking layer comprises aluminum oxide, wherein the hard mask layer comprises titanium nitride;
removing the hard mask layer and the blocking layer; and
performing an anneal process to drive lanthanum from the lanthanum containing layer to the high-k dielectric layer, wherein the lanthanum containing layer is exposed during the anneal process.

### Claim 2 (depends on 1)

The method of claim 1, wherein removing the hard mask layer and blocking layer comprises: performing a wet etch process using an etching solution including NH4, H2O2, and H2O.

### Claim 3 (depends on 2)

The method of claim 2, wherein the etching solution comprises NH4, H2O2, and H2O in a ratio of about 1:1:5.

### Claim 4 (depends on 2)

The method of claim 2, wherein the wet etch process is performed in a temperature range from about 20° C. to about 80° C. and for a time period in a range from about 150 seconds to about 300 seconds.

### Claim 5 (depends on 1)

The method of claim 1, the blocking layer having a thickness in a range from about 10 angstroms to about 30 angstroms.

### Claim 6 (depends on 5)

The method of claim 5, wherein forming the film stack comprises forming the blocking layer, forming the blocking layer comprises performing an atomic layer deposition (ALD) process using trimethylaluminum (TMA) and water vapor as precursors.

### Claim 7 (depends on 5)

The method of claim 5, wherein forming the film stack comprises forming the lanthanum containing layer, forming the lanthanum containing layer comprises performing an ALD process implementing a number of ALD cycles, the ALD cycles being in a range from 4 cycles to 8 cycles, the lanthanum containing layer comprising a lanthanum oxide layer.

### Claim 8

A method comprising:
forming a dielectric layer over a substrate, the dielectric layer having a recess exposing a channel region of the substrate;
forming a high-k dielectric layer over the dielectric layer and over sidewalls and a bottom of the recess;
forming a lanthanum containing layer over the high-k dielectric layer;
forming a blocking layer over the high-k dielectric layer, the blocking layer comprising aluminum oxide;
forming a hard mask layer over the high-k dielectric layer;
patterning the hard mask layer, blocking layer, and lanthanum containing layer;
after patterning the lanthanum containing layer, removing the hard mask layer and blocking layer; and
after removing the hard mask layer and the blocking layer, annealing to drive lanthanum from the lanthanum containing layer into the high-k dielectric layer, wherein the lanthanum containing layer extends above an upper surface of the dielectric layer while annealing.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the blocking layer comprises forming the aluminum oxide layer by an atomic layer deposition (ALD) process using trimethylaluminum (TMA) and water vapor as precursors.

### Claim 10 (depends on 9)

The method of claim 9, wherein the ALD process implements a number of ALD cycles, the ALD cycles being in a range from 10 cycles to 20 cycles.

### Claim 11 (depends on 8)

The method of claim 8, wherein the blocking layer has a thickness in a range from 10 angstroms to 30 angstroms.

### Claim 12 (depends on 8)

The method of claim 8, wherein removing the hard mask layer and the blocking layer comprises using a wet etch process.

### Claim 13 (depends on 12)

The method of claim 12, wherein the wet etch process is performed using an etching solution including NH4, H2O2, and H2O.

### Claim 14 (depends on 8)

The method of claim 8, further comprising, after removing the hard mask layer and the blocking layer.

### Claim 15 (depends on 8)

The method of claim 8, wherein the lanthanum containing layer has a thickness in a range from 3 angstroms to 6 angstroms.

### Claim 16 (depends on 8)

The method of claim 8, wherein the hard mask layer comprises titanium nitride.

### Claim 17

A method comprising:
forming a high-k dielectric layer over a first channel region and a second channel region of a substrate;
forming a lanthanum containing layer over the high-k dielectric layer over the first channel region and the second channel region;
forming a blocking layer over the lanthanum containing layer over the first channel region and the second channel region, wherein the blocking layer comprises aluminum oxide;
forming a masking layer over the blocking layer over the first channel region and the second channel region;
removing the masking layer, the blocking layer, and the lanthanum containing layer from over the second channel region;
removing the masking layer and the blocking layer from over the first channel region; and
after removing the masking layer and the blocking layer from over the first channel region, annealing to drive lanthanum from the lanthanum containing layer into the high-k dielectric layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising removing the lanthanum containing layer after performing the anneal.

### Claim 19 (depends on 17)

The method of claim 17, wherein the masking layer comprises titanium nitride.

### Claim 20 (depends on 17)

The method of claim 17, wherein the lanthanum containing layer comprises lanthanum oxide.