# US 10,504,794 B1 · Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor

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- Number: US 10,504,794 B1
- Document ID: US10504794B1
- Status: Granted
- Kind: B1
- Application number: 16/017,352
- Filed: 2018-06-25
- Published: 2019-12-26
- Granted: 2019-12-10
- Earliest claimed: 2018-06-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: ChoongHyun Lee; Kangguo Cheng; Juntao Li; Peng Xu
- Web page: https://patentgrep.com/patent/US10504794B1

## CPC

- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers.

## Claims

### Claim 1

A method for manufacturing a vertical transistor device, comprising:
forming a first plurality of fins in a first device region on a substrate;
forming a second plurality of fins in a second device region on the substrate;
forming a plurality of bottom source/drain regions on the substrate adjacent lower portions of each of the first and second plurality of fins in the first and second device regions;
forming a sacrificial layer in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions;
forming a bottom spacer layer on the plurality of bottom source/drain regions and the sacrificial layer;
forming a plurality of gate structures on the bottom spacer layer;
removing portions of the plurality of gate structures and of the bottom spacer layer to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region;
depositing a germanium oxide layer on the plurality of gate structures and on the exposed sacrificial layer and second bottom source/drain region; and
performing an annealing process to convert portions of the germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region to at least one of a plurality of silicide layers and a plurality of germanide layers.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the germanium oxide layer is a metal-doped germanium oxide layer.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the germanium oxide layer is conformally deposited.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the sacrificial layer is epitaxially grown.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the sacrificial layer comprises silicon germanium.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the annealing process is performed at a temperature in the range of about 500° C. to about 700° C.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the at least one of the plurality of silicide layers and the plurality of germanide layers are formed around the first and second plurality of fins on multiple sides of each of the first and second plurality of fins.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising forming a plurality of contacts to the plurality of bottom source/drain regions, wherein the at least one of the plurality of silicide layers and the plurality of germanide layers are formed around all sides of the plurality of contacts.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the first and second device regions respectively comprise n-type and p-type transistor regions.

### Claim 10 (depends on 1)

The method according to claim 1, further comprising covering a gate contact region with a mask during the removal of the portions of the plurality of gate structures and of the bottom spacer layer.

### Claim 11 (depends on 1)

The method according to claim 1, further comprising depositing a top spacer layer on the plurality of gate structures, wherein the top spacer layer is formed between the plurality of gate structures and at least a portion of the germanium oxide layer.

### Claim 12 (depends on 1)

The method according to claim 1, further comprising depositing a liner layer on unconverted portions of the germanium oxide layer and on the at least one of the plurality of silicide layers and the plurality of germanide layers.

### Claim 13 (depends on 1)

The method according to claim 1, further comprising:
conformally depositing a top spacer layer on the plurality of gate structures; and
conformally depositing a dielectric layer on the top spacer layer prior to the removal of the portions of the plurality of gate structures and of the bottom spacer layer.

### Claim 14 (depends on 1)

The method according to claim 1, wherein:
the removal of the portions of the plurality of gate structures and of the bottom spacer layer forms openings over the exposed sacrificial layer and second bottom source/drain region between remaining portions of the plurality of gate structures and the bottom spacer layer; and
the germanium oxide layer fills in the openings.

### Claim 15

A method for manufacturing a vertical transistor device, comprising:
forming a first plurality of fins in a first device region on a substrate;
forming a second plurality of fins in a second device region on the substrate;
epitaxially growing a plurality of bottom source/drain regions on the substrate adjacent lower portions of each of the first and second plurality of fins in the first and second device regions;
epitaxially growing a sacrificial layer in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions;
forming a plurality of gate structures on the plurality of bottom source/drain regions and the sacrificial layer;
removing portions of the plurality of gate structures to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region;
depositing a metal-doped germanium oxide layer on the plurality of gate structures and on the exposed sacrificial layer and second bottom source/drain region; and
performing an annealing process to convert portions of the metal-doped germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region to at least one of a plurality of silicide layers and a plurality of germanide layers.