# US 10,504,793 B2 · Hybrid-channel nano-sheet FETs

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- Number: US 10,504,793 B2
- Document ID: US10504793B2
- Status: Granted
- Kind: B2
- Application number: 15/903,167
- Filed: 2018-02-23
- Published: 2018-07-05
- Granted: 2019-12-10
- Earliest claimed: 2017-01-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Zhenxing Bi; Kangguo Cheng; Peng Xu; Wenyu Xu
- Web page: https://patentgrep.com/patent/US10504793B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region. First source/drain regions are grown in the first device region from exposed ends of the layers of the first channel material. Second source/drain regions are grown in the second device region from exposed ends of the layers of the second channel material.

## Claims

### Claim 1

A method of forming semiconductor devices:
forming first layer caps at ends of layers of first material in stacks of alternating layers of first material and second material;
forming second layer caps at ends of the layers of second material;
etching away the first layer caps in only a first device region;
etching away the second layer caps in only a second device region;
growing first source/drain regions in the first device region from exposed ends of the layers of the first material; and
growing second source/drain regions in the second device region from exposed ends of the layers of the second material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first material is silicon and wherein the second material is silicon germanium.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first source/drain regions are n-type doped and wherein the second source/drain regions are p-type doped.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming dummy gate structures on the stacks of alternating layers of first material and second material in the first and second device regions.

### Claim 5 (depends on 4)

The method of claim 4, further comprising etching away material of the stacks of alternating layers of first material and second material in areas that are not covered by the dummy gate structures.

### Claim 6 (depends on 4)

The method of claim 4, further comprising etching away the dummy gate structures after growing the first and second source/drain regions.

### Claim 7 (depends on 6)

The method of claim 6, further comprising etching away the layers of second material in the first device region and etching away the layers of first material in the second device region.

### Claim 8 (depends on 7)

The method of claim 7, further comprising depositing a first work function metal layer around the layers of first material in the first device region and depositing a second work function metal layer around the layers of second material in the second device region.

### Claim 9 (depends on 1)

The method of claim 1, wherein forming the first layer caps comprises oxidizing exposed portions of the first material.

### Claim 10 (depends on 1)

The method of claim 1, wherein forming the second layer caps comprises laterally etching the layers of the second material to form recesses and depositing a dielectric fill in the recesses.

### Claim 11 (depends on 1)

The method of claim 1, wherein the first layer caps are formed only on the layers of first material and the second layer caps are formed only on the layers of second material.

### Claim 12

A method of forming semiconductor devices:
forming first layer caps at ends of layers of first material in stacks of alternating layers of first material and second material by oxidizing exposed portions of the first material;
forming second layer caps at ends of the layers of second material;
etching away the first layer caps in a first device region;
etching away the second layer caps in a second device region;
growing first source/drain regions in the first device region from exposed ends of the layers of the first material; and
growing second source/drain regions in the second device region from exposed ends of the layers of the second material.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming dummy gate structures on the stacks of alternating layers of first material and second material in the first and second device regions.

### Claim 14 (depends on 13)

The method of claim 13, further comprising etching away the dummy gate structures after growing the first and second source/drain regions, etching away the layers of second material in the first device region, and etching away the layers of first material in the second device region.

### Claim 15 (depends on 12)

The method of claim 12, wherein forming the second layer caps comprises laterally etching the layers of the second material to form recesses and depositing a dielectric fill in the recesses.

### Claim 16

A method of forming semiconductor devices:
forming first layer caps at ends of layers of first material in stacks of alternating layers of first material and second material;
forming second layer caps at ends of the layers of second material by laterally etching the layers of the second material to form recesses and depositing a dielectric fill in the recesses;
etching away the first layer caps in a first device region;
etching away the second layer caps in a second device region;
growing first source/drain regions in the first device region from exposed ends of the layers of the first material; and
growing second source/drain regions in the second device region from exposed ends of the layers of the second material.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming dummy gate structures on the stacks of alternating layers of first material and second material in the first and second device regions.

### Claim 18 (depends on 17)

The method of claim 17, further comprising etching away the dummy gate structures after growing the first and second source/drain regions, etching away the layers of second material in the first device region, and etching away the layers of first material in the second device region.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the first layer caps comprises oxidizing exposed portions of the first material.