# US 10,504,792 B2 · Self-aligned nanowire formation using double patterning

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- Number: US 10,504,792 B2
- Document ID: US10504792B2
- Status: Granted
- Kind: B2
- Application number: 16/223,390
- Filed: 2018-12-18
- Published: 2019-04-25
- Granted: 2019-12-10
- Earliest claimed: 2014-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ching-Feng Fu; De-Fang Chen; Yu-Chan Yen; Chia-Ying Lee; Chun-Hung Lee; Huan-Just Lin
- Web page: https://patentgrep.com/patent/US10504792B2

## CPC

- H10D 84/016: {the components including vertical IGFETs}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10D 30/0318: {of vertical TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.

## Claims

### Claim 1

A method comprising:
performing a first etching process to etch a pattern-reservation layer, with remaining portions of the pattern-reservation layer forming pattern-reservation strips;
filling a filling material into spaces left by etched portions of the pattern-reservation layer;
performing a second etching process to etch the pattern-reservation strips and the filling material, wherein remaining portions of the pattern-reservation strips form pattern-reservation nanowires; and
etching a semiconductor substrate underlying the pattern-reservation nanowires, with the pattern-reservation nanowires being used as an etching mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second etching process comprises:
etching the filling material; and
etching the pattern-reservation strips, wherein the etching the filling material and the etching the pattern-reservation strips are separate etching processes.

### Claim 3 (depends on 1)

The method of claim 1, wherein the pattern-reservation strips have first lengthwise directions parallel to a first direction, and the second etching process is performed using elongated strips as an etching mask, and the elongated strips extend in a second direction non-parallel to the first direction, and the first direction and the second direction are parallel to a major surface of the semiconductor substrate.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first direction is perpendicular to the second direction.

### Claim 5 (depends on 1)

The method of claim 1, wherein in the first etching process, an oxide layer over the pattern-reservation layer is also etched to form oxide strips, and in the second etching process, the oxide strips are etched to form oxide nanowires.

### Claim 6 (depends on 5)

The method of claim 5, wherein the filling material is further filled into additional spaces left by etched portions of the oxide layer.

### Claim 7 (depends on 6)

The method of claim 6 further comprising, after the filling material is applied, performing a planarization process to level a top surface of the filling material with top surfaces of the oxide strips.

### Claim 8 (depends on 1)

The method of claim 1, wherein each of the first etching process and the second etching process comprises:
forming a mandrel layer;
etching the mandrel layer to form mandrel strips;
forming a spacer layer on the mandrel layer;
removing horizontal portions of the spacer layer and leaving vertical portions of the mandrel layer as spacers; and
removing the mandrel strips, wherein the spacers are used as an etching mask in respective ones of the first etching process and the second etching process.

### Claim 9 (depends on 8)

The method of claim 8, wherein longitudinal direction of the mandrel strips used in the first etching process is neither perpendicular to nor parallel to longitudinal direction of the mandrel strips used in the second etching process.

### Claim 10 (depends on 1)

The method of claim 1 further comprising rounding the pattern-reservation nanowires before the pattern-reservation nanowires are used to etch the semiconductor substrate.

### Claim 11 (depends on 1)

The method of claim 1 further comprising, after the first etching process and the second etching process, forming a photo resist over the semiconductor substrate, wherein in the etching the semiconductor substrate, a pattern of the photo resist and patterns of the pattern-reservation nanowires are transferred simultaneously into the semiconductor substrate.

### Claim 12

A method comprising:
forming a first amorphous silicon layer over a semiconductor substrate;
forming a patterned second amorphous silicon layer over the first amorphous silicon layer;
forming first spacers based on the patterned second amorphous silicon layer;
removing the patterned second amorphous silicon layer;
etching the first amorphous silicon layer using the first spacers as a first etching mask;
forming a patterned third amorphous silicon layer over the first amorphous silicon layer;
forming second spacers based on the patterned third amorphous silicon layer;
removing the patterned third amorphous silicon layer;
etching the first amorphous silicon layer using the second spacers as a second etching mask to form amorphous silicon nanowires; and
transferring patterns of the amorphous silicon nanowires into the semiconductor substrate to form semiconductor nanowires.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
before the transferring the patterns, oxidizing outer portions of the amorphous silicon nanowires to form oxide rings encircling inner portions of the amorphous silicon nanowires; and
removing the oxide rings.

### Claim 14 (depends on 12)

The method of claim 12 further comprising:
after the etching using the first etching mask, filling a filling material to embed remaining portions of the first amorphous silicon layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein in the etching using the second etching mask, the filling material is also etched.

### Claim 16 (depends on 12)

The method of claim 12 further comprising forming vertical transistors based on the semiconductor nanowires.

### Claim 17

A method comprising:
forming amorphous silicon nanowires;
rounding the amorphous silicon nanowires;
transferring patterns of the rounded amorphous silicon nanowires into a semiconductor substrate underlying the rounded amorphous silicon nanowires to form semiconductor nanowires; and
forming vertical transistors based on the semiconductor nanowires, with portions of the semiconductor nanowires acting as channel regions of the vertical transistors.

### Claim 18 (depends on 17)

The method of claim 17, wherein the forming the amorphous silicon nanowires comprises:
depositing an amorphous silicon layer; and
performing a first etching process and a second etching process to etch the amorphous silicon layer and to form the amorphous silicon nanowires.

### Claim 19 (depends on 18)

The method of claim 18, wherein in each of the first etching process and the second etching process, some portions of the amorphous silicon layer are removed.

### Claim 20 (depends on 18)

The method of claim 18, wherein the first etching process is performed using first strips as a first etching mask, and the second etching process is performed using second strips as a first etching mask, and the first strips and the second strips have longitudinal directions perpendicular to each other.