# US 10,504,790 B2 · Methods of forming conductive spacers for gate contacts and the resulting device

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- Number: US 10,504,790 B2
- Document ID: US10504790B2
- Status: Granted
- Kind: B2
- Application number: 15/658,524
- Filed: 2017-07-25
- Published: 2019-01-31
- Granted: 2019-12-10
- Earliest claimed: 2017-07-25
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Ruilong Xie; Lars W. Liebmann; Bipul C. Paul; Daniel Chanemougame; Nigel G. Cave
- Web page: https://patentgrep.com/patent/US10504790B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/834: {comprising FinFETs}
- H10W 20/034: {bottomless barrier, adhesion or liner layers}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/076: {in via holes or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a first gate structure above a first region of a semiconducting substrate. A first sidewall spacer is formed adjacent the first gate structure. The first gate structure and the first sidewall spacer are recessed to define a first gate contact cavity. A second sidewall spacer is formed in the first gate contact cavity. A first conductive gate contact is formed in the first gate contact cavity. The second sidewall spacer is removed to define a first spacer cavity. A conductive material is formed in the first spacer cavity to form a first conductive spacer contacting the first conductive gate contact.

## Claims

### Claim 1

A method, comprising:
forming a first gate structure above a first region of a semiconducting substrate;
forming a first sidewall spacer adjacent said first gate structure;
forming a first dielectric layer adjacent said first sidewall spacer;
recessing said first gate structure and said first sidewall spacer to define a first gate contact cavity;
forming a second sidewall spacer in said first gate contact cavity;
forming a first conductive gate contact in said first gate contact cavity;
removing said second sidewall spacer after forming said first conductive gate contact to expose an upper surface of said first sidewall spacer and define a first spacer cavity between said first dielectric layer and said first conductive gate contact; and
forming a conductive material in said first spacer cavity to form a first conductive spacer contacting said first conductive gate contact and said upper surface of said first sidewall spacer, wherein said first sidewall spacer covers an entire sidewall of said first gate structure after said conductive material is formed.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a first gate cap layer in said first gate contact cavity;
forming a second dielectric layer above said first gate cap layer;
forming a second gate contact cavity in said second dielectric layer so as to thereby expose said first gate cap layer;
removing said first gate cap layer; and
forming said first conductive gate contact after removing said first gate cap layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming said first conductive gate contact further comprises forming said first conductive gate contact in said first and second gate contact cavities, and the method further comprises:
recessing said first conductive gate contact to expose at least a portion of said second sidewall spacer; and
removing said second sidewall spacer after recessing said first conductive gate contact.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
forming a third dielectric layer above said first conductive gate contact and said first conductive spacer; and
forming a second conductive gate contact in said third dielectric layer contacting said first conductive gate contact.

### Claim 5 (depends on 4)

The method of claim 4, wherein said second conductive gate contact contacts at least a portion of said first conductive spacer.

### Claim 6 (depends on 3)

The method of claim 3, further comprising:
forming a first source/drain (SD) region adjacent said first gate structure; and
forming a first SD contact contacting said first SD region, wherein said first conductive spacer contacts said first SD contact and said first gate contact.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming said first dielectric layer above said first gate structure; and
planarizing said first dielectric layer to expose said first gate structure and said first sidewall spacer prior to recessing said first gate structure and said first sidewall spacer, wherein said first gate contact cavity is defined in said first dielectric layer.

### Claim 8

A method, comprising:
forming a plurality of gate structures above a semiconducting substrate;
forming first sidewall spacers adjacent each of said plurality of gate structures;
forming a first dielectric layer adjacent said first sidewall spacers;
recessing said plurality of gate structures and said first sidewall spacers to define first gate contact cavities;
forming second sidewall spacers in said first gate contact cavities;
forming first conductive gate contacts in said first gate contact cavities;
forming a mask layer above a first subset of said plurality of gate structures;
removing said second sidewall spacers of a second subset of said plurality of gate structures not covered by said mask layer after forming said first conductive gate contact to expose an upper surface of said first sidewall spacers and to define first spacer cavities between said first dielectric layer and said first conductive gate contacts; and
forming a conductive material in said first spacer cavities to form first conductive spacers contacting said first conductive gate contacts and said upper surfaces of said first sidewall spacers for said second subset of said plurality of gate structures, wherein said first sidewall spacers cover entire sidewalls of said first gate structures after said conductive material is formed.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
forming first gate cap layers in said first gate contact cavities;
forming said first dielectric layer above said first gate cap layers;
forming second gate contact cavities in said first dielectric layer so as to thereby expose said first gate cap layers;
removing said first gate cap layers; and
forming said first conductive gate contacts after removing said first gate cap layers.

### Claim 10 (depends on 8)

The method of claim 8, wherein forming said first conductive gate contacts further comprises forming said first conductive gate contacts in said first and second gate contact cavities, wherein said mask layer is formed above said first conductive gate contacts of said first subset of said plurality of gate structures.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
recessing said first conductive gate contacts of said second subset of said plurality of gate structures to expose at least a portion of said second sidewall spacers; and
removing said second sidewall spacers after recessing said first conductive gate contacts.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
forming a second dielectric layer above said first conductive gate contacts and said first conductive spacers; and
forming second conductive gate contacts in said second dielectric layer contacting said first conductive gate contacts for said second subset of said plurality of gate structures.

### Claim 13 (depends on 12)

The method of claim 12, wherein said second conductive gate contacts contact at least a portion of said first conductive spacers.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
forming first source/drain (SD) regions adjacent said plurality of gate structures;
forming first SD contacts contacting said first SD region, wherein said first conductive spacers in said second subset of the plurality of gate structures contacts said first SD contacts and said first gate contacts.

### Claim 15 (depends on 8)

The method of claim 8, wherein said first subset of said plurality of gate structures is formed above an active region, and said second subset of said plurality of gate structures is formed above an isolation region outside said active region.

### Claim 16 (depends on 8)

The method of claim 8, further comprising:
forming said first dielectric layer above said plurality of gate structures; and
planarizing said first dielectric layer to expose said first gate structures and said first sidewall spacers prior to recessing said first gate structures and said first sidewall spacers, wherein said first gate contact cavities are defined in said first dielectric layer.

### Claim 17

A device, comprising:
a first gate structure positioned above a semiconducting substrate;
a first sidewall spacer positioned adjacent said first gate structure;
a first conductive gate contact contacting said first gate structure and an upper surface of said first sidewall spacer;
a first conductive spacer contacting said first sidewall spacer and a sidewall of said first conductive gate contact, wherein said first conductive spacer does not contact said first gate structure;
a second gate structure positioned above said semiconducting substrate;
a second sidewall spacer positioned adjacent said second gate structure;
a second conductive gate contact contacting said second gate structure and an upper surface of said second sidewall spacer; a first source/drain (SD) region positioned adjacent said second gate structure;
a first SD contact contacting said first SD region; and
a second conductive spacer contacting said second sidewall spacer and a sidewall of said first conductive gate contact, wherein said first conductive spacer contacts said first SD contact and said first gate structure.

### Claim 18 (depends on 17)

The device of claim 17, further comprising an active region defined in said semiconductor substrate by an isolation structure, wherein said first conductive gate structure is formed above said isolation structure outside said active region.

### Claim 19 (depends on 17)

The device of claim 17, further comprising:
a dielectric layer positioned above said first conductive gate contact; and
a second conductive gate contact positioned in said dielectric layer, wherein said second conductive gate contact contacts said first conductive gate contact and at least a portion of said first conductive spacer.