# US 10,504,789 B1 · Pre-deposition treatment for FET technology and devices formed thereby

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- Number: US 10,504,789 B1
- Document ID: US10504789B1
- Status: Granted
- Kind: B1
- Application number: 15/992,556
- Filed: 2018-05-30
- Published: 2019-12-05
- Granted: 2019-12-10
- Earliest claimed: 2018-05-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Cheng-Yen Tsai; Chung-Chiang Wu; Tai-Wei Hwang; Hung-Chin Chung; Wei-Chin Lee; Da-Yuan Lee; Ching-Hwanq Su; Yin-Chuan Chuang; Kuan-Ting Liu
- Web page: https://patentgrep.com/patent/US10504789B1

## CPC

- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10P 14/668: {the materials being characterised by the deposition precursor materials}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

## Claims

### Claim 1

A method for semiconductor processing, the method comprising:
exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first metal-containing layer and the second metal-containing layer, the first device and the second device being on a substrate, the first device comprising a first gate structure including the first metal-containing layer, the second device comprising a second gate structure including the second metal-containing layer, the first metal-containing layer being a different material from the second metal-containing layer;
exposing the monolayers on the first metal-containing layer and the second metal-containing layer to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers on the first metal-containing layer and the second metal-containing layer; and
forming a third metal-containing layer on the —OH terminated surfaces of the monolayers on the first metal-containing layer and the second metal-containing layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the reactant comprises an aluminum-based precursor, and the aluminum-based precursor comprises trimethylaluminum (TMA), triethylaluminum (TEA), dimethylethylaminealane (DMEAA), dimethylaluminum hydride (DMAH), tritertiarybutyl aluminium (TTBA), tri-isobutyl-aluminum (TIBA), triimethylylamine alane (TMAA), trimethylamine alane (TEAA), an aluminum-containing metalorganic precursor, or a combination thereof.

### Claim 3 (depends on 2)

The method of claim 2, wherein the monolayers on the first metal-containing layer and the second metal-containing layer are aluminum oxide.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first device and the second device are different type devices selected from a group comprising: an n-type ultra-low threshold voltage (N-uLVT) device, an n-type low threshold voltage (N-LVT) device, an n-type standard threshold voltage (N-SVT), an n-type high threshold voltage (N-HVT) device, a p-type ultra-low threshold voltage (P-uLVT) device, a p-type low threshold voltage (P-LVT) device, a p-type standard threshold voltage (P-SVT), and a p-type high threshold voltage (P-HVT) device.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first metal-containing layer is TaN and third metal-containing layer is TiN.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second metal-containing layer comprises TiAlC and TiAlO.

### Claim 7 (depends on 1)

The method of claim 1, wherein the reactant comprises a silicon-based precursor, and the silicon-based precursor comprises silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H10), or a combination thereof.

### Claim 8 (depends on 7)

The method of claim 7, wherein the monolayers on the first metal-containing layer and the second metal-containing layer are silicon oxide.

### Claim 9 (depends on 1)

The method of claim 1, wherein the respective monolayers on the first metal-containing layer and the second metal-containing layer are formed by an atomic layer deposition (ALD) process, and the third metal-containing layer is formed by an ALD process.

### Claim 10

A method for semiconductor processing, the method comprising:
forming a first layer in a first trench and a second trench on a substrate;
forming a second layer over the first layer in the second trench, the first layer in the first trench being free of the second layer;
forming a pre-treatment layer on the first layer in the first trench and the second layer in the second trench, the pre-treatment layer comprising a monolayer of aluminum oxide or silicon oxide;
terminating the pre-treatment layer with hydroxyl groups to form a hydroxyl group terminated surface over the pre-treatment layer in the first trench and the second trench; and
forming a metal-containing layer on the hydroxyl group terminated surface in the first trench and the second trench.

### Claim 11 (depends on 10)

The method of claim 10, wherein terminating the pre-treatment layer comprises exposing the pre-treatment layer to an oxidant.

### Claim 12 (depends on 10)

The method of claim 10, wherein a thickness of the metal-containing layer in the first trench is substantially the same as a thickness of the metal-containing layer in the second trench.

### Claim 13 (depends on 10)

The method of claim 10, wherein forming the monolayer of aluminum oxide or silicon oxide comprises:
forming a monolayer of aluminum performed in part by exposing the first layer and the second layer to trimethylaluminum (TMA) or triethylaluminum (TEA); and
removing the substrate from a process chamber prior to forming the metal-containing layer.

### Claim 14 (depends on 10)

The method of claim 10, wherein forming the monolayer of aluminum oxide or silicon oxide comprises:
forming a monolayer of silicon performed in part by exposing the first layer and the second layer to a silane or a disilane; and
removing the substrate from a process chamber prior to forming the metal-containing layer.

### Claim 15 (depends on 10)

The method of claim 10, wherein the first layer comprises tantalum nitride, and wherein the second layer comprises a titanium-containing layer.

### Claim 16

A method for semiconductor processing, the method comprising:
forming a first metal-containing layer in a first trench and a second trench on a substrate;
forming a second metal-containing layer over the first metal-containing layer in the second trench, the first trench being free of the second metal-containing layer, the first metal-containing layer and the second metal-containing layer being different materials;
exposing the first metal-containing layer and the second metal-containing layer to a reactant to form a monolayer on the first metal-containing layer in the first trench and on the second metal-containing layer in the second trench;
exposing the monolayer to an oxidant to form an oxide monolayer having a hydroxyl group (—OH) terminated surface; and
forming a third metal-containing layer on the oxide monolayer in the first trench and the second trench.

### Claim 17 (depends on 16)

The method of claim 16, wherein a thickness of the third metal-containing layer in the first trench is substantially the same as a thickness of the third metal-containing layer in the second trench.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
forming a first gate electrode over the third metal-containing layer in the first trench to form a first transistor; and
forming a second gate electrode over the third metal-containing layer in the first trench to form a second transistor, wherein the first transistor and the second transistor comprise a same conductive type of transistor, wherein a threshold voltage of the first transistor is different than a threshold voltage of the second transistor.

### Claim 19 (depends on 16)

The method of claim 16, wherein the oxide monolayer comprises aluminum oxide.

### Claim 20 (depends on 16)

The method of claim 16, wherein the oxide monolayer comprises silicon oxide.