# US 10,504,786 B2 · Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,786 B2
- Document ID: US10504786B2
- Status: Granted
- Kind: B2
- Application number: 15/463,972
- Filed: 2017-03-20
- Published: 2017-07-06
- Granted: 2019-12-10
- Earliest claimed: 2015-06-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Veeraraghavan S. Basker; Kangguo Cheng; Theodorus E. Standaert
- Web page: https://patentgrep.com/patent/US10504786B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/274: {using seed materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.

## Claims

### Claim 1

A method for forming a semiconductor structure comprising:
providing a semiconductor substrate;
forming at least one mandrel on the semiconductor substrate;
forming a first sidewall image transfer (SIT) spacer on opposing sidewalls of the at least one mandrel;
forming, after the forming of the at least one mandrel and the first SIT spacer, a mandrel SIT spacer on a sidewall of each of the first SIT spacers, wherein the at least one mandrel and the mandrel SIT spacer have a same width and comprise a same mandrel material as each other, and the mandrel material is selected from the group consisting of polysilicon, amorphous silicon and amorphous carbon;
forming a second SIT spacer having a sidewall directly contacting a sidewall of each of the mandrel SIT spacers, wherein the first and second SIT spacers comprise a spacer material that differs from the mandrel material and have a same width, wherein the width of the first and second SIT spacers is less than the width of the at least one mandrel and the mandrel SIT spacer;
removing, at the same time, the at least one mandrel and each of the mandrel SIT spacers from the sidewalls of the first and second SIT spacers, thereby defining a pattern comprising the first SIT spacers and the second SIT spacers on the semiconductor substrate; and
etching the semiconductor substrate using the first SIT spacers and the second SIT spacers as an etching mask to transfer the pattern of the first SIT spacers and the second SIT spacers into the semiconductor substrate to form a plurality of semiconductor fins from the semiconductor substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a pad layer on the semiconductor substrate prior to forming the at least one mandrel.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first SIT spacers and the second SIT spacers comprise a same spacer material as each other.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first SIT spacers comprise a first spacer material, and the second SIT spacers comprise a second spacer material that differs from the first spacer material.

### Claim 5 (depends on 1)

The method of claim 1, wherein the semiconductor substrate is a bulk semiconductor substrate, and wherein the bulk semiconductor is etched using the first SIT spacers and the second SIT spacers as the etching mask to thereby form the plurality of trenches in the bulk semiconductor substrate, wherein the trenches define a plurality of semiconductor fins that are integral with the bulk semiconductor substrate.

### Claim 6 (depends on 1)

The method of claim 1, wherein the at least one mandrel, the mandrel SIT spacer, the first SIT spacers and the second SIT spacers have topmost surfaces and bottommost surfaces that are coplanar with each other.

### Claim 7 (depends on 1)

The method of claim 1, wherein the removing the at least one mandrel and the mandrel SIT spacers is utilizing an anisotropic etch.

### Claim 8 (depends on 1)

The method of claim 1, further comprising removing the first and second SIT spacers from the semiconductor fins.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a field effect transistor on physically exposed surfaces of each semiconductor fin.

### Claim 10 (depends on 2)

The method of claim 2, wherein prior to the etching the semiconductor substrate, the pad layer is etched utilizing the first SIT spacers and the second SIT spacers as an etching mask.

### Claim 11 (depends on 10)

The method of claim 10, further comprising removing the first and second SIT spacers and remaining portions of the pad layer from the semiconductor fins.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming a field effect transistor on physically exposed surfaces of each semiconductor fin.