# US 10,504,784 B2 · Inductor structure for integrated circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,784 B2
- Document ID: US10504784B2
- Status: Granted
- Kind: B2
- Application number: 15/793,127
- Filed: 2017-10-25
- Published: 2019-04-25
- Granted: 2019-12-10
- Earliest claimed: 2017-10-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Han Huang; Ching-Chun Wang; Dun-Nian Yaung; Hsing-Chih Lin; Jen-Cheng Liu; Min-Feng Kao
- Web page: https://patentgrep.com/patent/US10504784B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H01F 17/0013: {with stacked layers}
- H01F 41/041: {Printed circuit coils (apparatus or processes for manufacturing printed circuits in general H05K3/00)}
- H10D 1/20: Inductors
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 72/011: {Apparatus therefor}
- H10W 90/00: Package configurations
- H01F 2017/002: {Details of via holes for interconnecting the layers}
- H01F 2017/004: {with the coil helically wound around an axis without a core}
- H01F 2017/0086: {on semiconductor substrate}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 90/792: {between multiple chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure, in some embodiments, relates to an integrated circuit having an inductor with one or more turns arranged along vertical planes that intersect an underlying substrate. In some embodiments, the integrated circuit includes a plurality of conductive routing layers having conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate. The plurality of conductive routing layers define an inductor having one or more turns respectively including a vertically extending segment arranged along a plane that intersects the first substrate. The vertically extending segment has a plurality of the conductive wires and the conductive vias.

## Claims

### Claim 1

An integrated circuit, comprising:
a plurality of conductive routing layers comprising conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate;
wherein the plurality of conductive routing layers define an inductor having one or more turns respectively comprising a vertically extending segment arranged along a plane that intersects the first substrate;
wherein the vertically extending segment comprises a plurality of the conductive wires and the conductive vias;
wherein the vertically extending segment comprises:
a first conductive interconnect via having first sidewalls angled to increase a first width of the first conductive interconnect via as a distance from the first substrate increases; and
a second conductive interconnect via having second sidewalls angled to decrease a second width of the second conductive interconnect via as the distance from the first substrate increases.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the one or more turns respectively wind around an axis that extends along a line that does not intersect a first surface of the first substrate facing one of the one or more dielectric structures.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive routing layers comprise a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure comprising a plurality of stacked ILD layers.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, further comprising:
a second substrate; and
a second ILD structure disposed between the second substrate and the first ILD structure and surrounding a second plurality of conductive interconnect layers, wherein the plurality of conductive routing layers further comprise the second plurality of conductive interconnect layers.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, further comprising:
a first ILD structure arranged along a first surface of the first substrate and surrounding a first plurality of conductive interconnect layers; and
a plurality of redistribution layers arranged along a second surface of the first substrate and configured to couple the first plurality of conductive interconnect layers to a bond pad, wherein the plurality of redistribution layers comprise the plurality of conductive routing layers.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein the vertically extending segment comprises a through-substrate via (TSV) extending through the first substrate.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of conductive wires defining the vertically extending segment increase in size from a third width to a fourth width and decrease in size from the fourth width to a fifth width along a line intersecting a first surface of the first substrate facing one of the one or more dielectric structures.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the one or more turns extend through the first substrate.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, further comprising:
a first ILD structure arranged along a first surface of the first substrate, wherein the first ILD structure surrounds a first plurality of conductive interconnect layers;
through-substrate vias (TSVs) extending through the first substrate;
an additional dielectric structure arranged along a second surface of the first substrate opposite the first surface, wherein the additional dielectric structure surrounds a plurality of redistribution layers coupled to the first plurality of conductive interconnect layers by the TSVs; and
wherein the vertically extending segment is defined by the first plurality of conductive interconnect layers, the TSVs, and the plurality of redistribution layers.

### Claim 10

A semiconductor device, comprising:
a first substrate;
a passivation layer disposed along a first side of the first substrate;
one or more redistribution layers disposed within one or more dielectric structures and separated from the first side of the first substrate by the passivation layer;
a first plurality of conductive interconnect layers within a first inter-level dielectric (ILD) structure along a second side of the first substrate opposing the first side;
a through-substrate-via (TSV) extending through the first substrate and coupling the first plurality of conductive interconnect layers to the one or more redistribution layers; and
wherein the one or more redistribution layers define at least a part of an inductor having one or more turns that wind around an axis extending parallel to a first surface of the first substrate facing one of the one or more dielectric structures.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the one or more turns comprise:
a first turn including a first pair of vertically extending segments respectively comprising a first plurality of conductive wires and conductive vias;
a second turn including a second pair of vertically extending segments respectively comprising a second plurality of conductive wires and conductive vias; and
wherein one of the first pair of vertically extending segments is coupled to one of the second pair of vertically extending segments by a horizontally extending segment comprising a conductive wire.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the TSVs have a width that increases as a distance from the passivation layer decreases.

### Claim 13 (depends on 10)

The semiconductor device of claim 10,
wherein the inductor is further defined by comprise the first plurality of conductive interconnect layers.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, further comprising:
a second substrate;
a second ILD structure between the second substrate and the first ILD structure; and
a second plurality of conductive interconnect layers within the second ILD structure, wherein the inductor is further defined by the second plurality of conductive interconnect layers.

### Claim 15 (depends on 14)

The semiconductor device of claim 14,
wherein the inductor is further defined by the TSVs; and
wherein at least one of the TSVs directly contacts one of the first plurality of conductive interconnect layers defining a bottommost surface of the inductor.

### Claim 16 (depends on 10)

The semiconductor device of claim 10,
wherein the one or more turns are arranged completely over the first side of the first substrate.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein all of the TSVs that define the inductor are arranged along outermost lateral edges of the inductor.

### Claim 18

An integrated circuit, comprising:
a plurality of conductive routing layers comprising conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate;
wherein the plurality of conductive routing layers define an inductor having one or more turns respectively comprising a vertically extending segment arranged along a plane that intersects the first substrate;
wherein the plurality of conductive routing layers comprise:
a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure comprising a plurality of stacked ILD layers on the first substrate; and
a second ILD structure disposed between a second substrate and the first ILD structure and surrounding a second plurality of conductive interconnect layers, wherein the plurality of conductive routing layers further comprise the second plurality of conductive interconnect layers.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein the plurality of conductive routing layers comprise:
a first via contacting a top of a first interconnect wire and coupling the first interconnect wire to a second interconnect wire, wherein the second interconnect wire defines a top of a first turn of the one or more turns; and
a second via contacting the top of the first interconnect wire and coupling the first interconnect wire to a third interconnect wire defining a top of a second turn of the one or more turns.

### Claim 20 (depends on 18)

The integrated circuit of claim 18, wherein the plurality of conductive routing layers comprise a through-substrate via coupling a first interconnect wire defining a top of the inductor to a second interconnect wire defining a bottom of the inductor.