# US 10,504,782 B2 · Fin Field-Effect Transistor device and method of forming the same

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- Number: US 10,504,782 B2
- Document ID: US10504782B2
- Status: Granted
- Kind: B2
- Application number: 16/104,006
- Filed: 2018-08-16
- Published: 2019-04-04
- Granted: 2019-12-10
- Earliest claimed: 2017-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shich-Chang Suen; Kei-Wei Chen; Liang-Guang Chen
- Web page: https://patentgrep.com/patent/US10504782B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/6302: {Non-deposition formation processes}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6504: {In-situ cleaning}
- H10P 14/6512: {by exposure to a gas or vapour}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/6922: {the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/42: Vias, e.g. via plugs
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10P 14/61: using masks
- H10P 50/266: {by vapour etching only}
- H10P 50/667: {by liquid etching only}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.

## Claims

### Claim 1

A method comprising:
forming a first gate structure over a substrate, wherein the first gate structure is surrounded by a first dielectric layer;
forming a mask structure over the first gate structure and over the first dielectric layer, wherein forming the mask structure comprises:
selectively forming a first capping layer over an upper surface of the first gate structure; and
forming a second dielectric layer around the first capping layer;
forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure;
removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and
filling the recess with a conductive material.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the mask structure further comprises after forming the first capping layer and before forming the second dielectric layer, selectively forming a second capping layer over the first capping layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first capping layer and the second capping layer are formed of a same material that is different from the first dielectric layer, and wherein sidewalls of the first capping layer are aligned with respective sidewalls of the second capping layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein selectively forming the first capping layer comprises:
forming a surface treated layer over the first dielectric layer, wherein the surface treated layer covers an upper surface of the first dielectric layer and exposes the upper surface of the first gate structure, wherein a first deposition rate of the first capping layer on the surface treated layer is lower than a second deposition rate of the first capping layer on the first gate structure; and
supplying one or more precursors for forming the first capping layer to the exposed upper surface of the first gate structure and to the surface treated layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the first capping layer comprises silicon nitride, and the first dielectric layer comprises silicon oxide.

### Claim 6 (depends on 4)

The method of claim 4, wherein supplying one or more precursors comprises supplying a first precursor comprising dichlorosilane (H2SiCl2) and a second precursor comprising ammonia (NH3) to the exposed upper surface of the first gate structure and to the surface treated layer.

### Claim 7 (depends on 4)

The method of claim 4, wherein forming the surface treated layer comprises converting an upper portion of the first dielectric layer into the surface treated layer by performing an in-situ HF vapor cleaning process.

### Claim 8 (depends on 7)

The method of claim 7, wherein performing the in-situ HF vapor cleaning process comprises supplying a vapor comprising azeotropic HF/H2O, azeotropic HCl/H2O, H2O, and high purity isopropyl alcohol (IPA) to a surface of the first dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first capping layer comprises a metal, and wherein forming the mask structure further comprises:
growing carbon nanotubes on the first capping layer after selectively forming the first capping layer and before forming the second dielectric layer;
after forming the second dielectric layer, removing the carbon nanotubes and the first capping layer to form an opening in the second dielectric layer; and
filling the opening with a third dielectric material.

### Claim 10 (depends on 9)

The method of claim 9, wherein the metal is cobalt or iron.

### Claim 11 (depends on 10)

The method of claim 10, wherein growing carbon nanotubes comprises supplying a precursor comprising acetylene to an upper surface of the first capping layer.

### Claim 12

A method comprising:
forming a first gate over a substrate;
forming a second gate over the substrate and adjacent to the first gate, the first gate and the second gate being embedded in a first dielectric material;
forming a capping layer on the first gate and on the second gate;
growing carbon nanotubes on the capping layer;
forming a second dielectric material over the first dielectric material and around the carbon nanotubes;
removing the carbon nanotubes and the capping layer to form first recesses in the second dielectric material;
filling the first recesses with a third dielectric material, thereby forming a first hard mask over the first gate and a second hard mask over the second gate;
removing a portion of the second dielectric material between the first hard mask and the second hard mask and a portion of the first dielectric material between the first gate and the second gate, thereby forming a second recess; and
filling the second recess with a conductive material.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the capping layer comprises selectively forming a metal layer over a first upper surface of the first gate and over a second upper surface of the second gate.

### Claim 14 (depends on 12)

The method of claim 12, wherein growing the carbon nanotubes comprises supplying a gas comprising carbon to the capping layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein removing the carbon nanotubes and the capping layer comprises:
removing the carbon nanotubes in a first etching process; and
after removing the carbon nanotubes, removing the capping layer in a second etching process different from the first etching process.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first etching process is a dry etch process, and the second etching process is a wet etch process.

### Claim 17

A semiconductor device comprising:
a first gate over a substrate;
first gate spacers along sidewalls of the first gate;
a second gate over the substrate and adjacent to the first gate;
second gate spacers along sidewalls of the second gate, the first gate and the second gate being surrounded by a first dielectric material;
a first capping layer over a first upper surface of the first gate and over a second upper surface of the second gate, the first capping layer and the first dielectric material comprising different materials;
a second capping layer over the first capping layer, the first capping layer and the second capping layer comprising a same dielectric material, sidewalls of the first capping layer being aligned with respective sidewalls of the second capping layer;
a second dielectric material over the first dielectric material, the second dielectric material surrounding the first capping layer and the second capping layer; and
an electrically conductive material between the first gate and the second gate, the electrically conductive material extending from a first one of the first gate spacers to a first one of the second gate spacers.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first capping layer and the second capping layer comprise silicon nitride, and the first dielectric material comprises silicon oxide.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the first capping layer is a lowermost capping layer, and the second capping layer is an uppermost capping layer, wherein an upper surface of the second dielectric material is level with an upper surface of the second capping layer.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein an upper surface of the electrically conductive material is level with the upper surface of the second dielectric material.