# US 10,504,777 B2 · Method of manufacturing wafer level low melting temperature interconnections

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- Number: US 10,504,777 B2
- Document ID: US10504777B2
- Status: Granted
- Kind: B2
- Application number: 15/895,512
- Filed: 2018-02-13
- Published: 2019-08-15
- Granted: 2019-12-10
- Earliest claimed: 2018-02-13
- Assignees: Raytheon Company
- Applicants: Raytheon Company
- Inventors: Sean P. Kilcoyne; Eric R. Miller; George Grama
- Web page: https://patentgrep.com/patent/US10504777B2

## CPC

- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- C23C 18/1653: {Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating}
- C23C 18/168: {Control of temperature, e.g. temperature of bath, substrate}
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- H05K 3/424: {by direct electroplating}
- H10P 70/237: {the processing being a planarisation of insulating layers}
- H10W 20/043: {for electroplating}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 20/0425: {comprising multiple stacked seed or nucleation layers}
- H10W 72/019: {of bond pads}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/0198: {batch processes}
- H10W 72/07331: {Connecting techniques}
- H10W 72/90: Bond pads, in general
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/016: {Cleaning}
- H10W 80/031: {Changing or setting shapes of the pads}
- H10W 80/037: {by mechanical treatment, e.g. by cutting, pressing or stamping}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

## Claims

### Claim 1

A method of manufacturing an array of planar wafer level metal posts comprising:
plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer;
stripping the PR pattern mold from the substrate and array of posts;
after the step of stripping the PR pattern mold, applying a PR layer around each of the posts;
after the step of applying a PR layer, etching a metal seed layer on the substrate to singulate the array of posts;
applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer and around the array of posts extending from the surface; and
applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

### Claim 2 (depends on 1)

The method of claim 1 further comprising, after the step of etching a metal seed layer, stripping the PR layer.

### Claim 3 (depends on 1)

The method of claim 1 wherein in the step of applying an oxide layer, the oxide layer is applied at a temperature of between 127 degrees Celsius and 147 degrees Celsius.

### Claim 4 (depends on 1)

The method of claim 1 wherein in the step of applying an oxide layer, the oxide layer is applied at a temperature of between 135 degrees Celsius and 139 degrees Celsius.

### Claim 5 (depends on 1)

The method of claim 1 wherein the posts are comprised of Indium.

### Claim 6

A method of manufacturing a bonded wafer assembly with Indium interconnections comprising:
a) providing a first wafer with a substrate layer, an insulating layer, and a metal seed layer, the metal seed layer connected to the substrate layer by vias extending through a first plurality of holes in the insulating layer;
b) applying a photoresist (PR) pattern mold over the metal seed layer such that a second plurality of holes through the PR pattern mold align with the vias;
c) plating Indium within the second plurality of holes in the PR pattern mold to form an array of Indium posts on the first wafer;
d) stripping the PR pattern mold;
e) etching a portion of the metal seed layer to singulate the array of Indium posts;
f) applying an oxide layer, at a temperature below 150 degrees Celsius, over a surface of the first wafer;
g) applying chemical-mechanical polishing (CMP) to form a planar surface, the planar surface including the array of Indium posts and the oxide layer;
h) performing steps a)-g) to create a second wafer;
i) aligning the Indium posts of the first and second wafers; and
j) bonding the first wafer and the second wafer together to form the bonded wafer assembly.

### Claim 7 (depends on 6)

The method of claim 6 wherein in step (j), the bonding is done through a low temperature annealing process.

### Claim 8 (depends on 6)

The method of claim 6 further comprising, after step (d) and before step (e), placing a PR layer around each of the Indium posts.

### Claim 9 (depends on 8)

The method of claim 8 further comprising, after step (e) and before step (f), stripping the PR layer.

### Claim 10 (depends on 8)

The method of claim 8 further comprising, after step (g), placing a second PR layer over exposed surfaces of the array of Indium posts.

### Claim 11 (depends on 10)

The method of claim 10 further comprising, after the step of placing a second PR layer, cleaning an exposed surface of the oxide layer.

### Claim 12 (depends on 11)

The method of claim 11 wherein cleaning an exposed surface of the oxide layer is done by applying HCl.

### Claim 13 (depends on 6)

The method of claim 6 wherein in the step (f), the oxide layer is applied at a temperature of between 127 degrees Celsius and 147 degrees Celsius.

### Claim 14 (depends on 6)

The method of claim 6 wherein in the step (f), the oxide layer is applied at a temperature of between 135 degrees Celsius and 139 degrees Celsius.

### Claim 15

A method of manufacturing an array of planar wafer level metal posts comprising:
plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer;
stripping the PR pattern mold from the substrate and array of posts;
after the step of stripping the PR pattern mold, applying a PR layer around each of the posts;
applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer and around the array of posts extending from the surface;
applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts; and
after the step of applying CMP, protecting exposed surfaces of the array of posts with a second PR layer.

### Claim 16 (depends on 15)

The method of claim 15 further comprising, after the step of protecting exposed surfaces of the array of posts, cleaning a surface of the oxide layer.

### Claim 17 (depends on 16)

The method of claim 16 wherein in the step of cleaning a surface of the oxide layer, the surface is cleaned by applying HCl.