# US 10,504,752 B2 · Integrated passive device package and methods of forming same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,752 B2
- Document ID: US10504752B2
- Status: Granted
- Kind: B2
- Application number: 15/911,893
- Filed: 2018-03-05
- Published: 2018-07-12
- Granted: 2019-12-10
- Earliest claimed: 2016-02-10
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Feng-Cheng Hsu; Shuo-Mao Chen; Jui-Pin Hung; Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US10504752B2

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/073: {of die-attach connectors}
- H10W 74/016: {using moulds}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/0198: {batch processes}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/014: {using batch processing}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The package further includes redistribution layers (RDLs) extending laterally past edges of the first die and the second die. The RDLs include an input/output (I/O) contact electrically connected to the first die and the second die, and the I/O contact is exposed at a sidewall of the device package substantially perpendicular to a surface of the molding compound opposite the RDLs.

## Claims

### Claim 1

A method comprising:
encapsulating a plurality of passive device dies and an additional passive device die in a first molding compound, wherein all dies encapsulated by the first molding compound are substantially free of any active regions;
forming first redistribution layers (RDLs) extending laterally past edges of the plurality of passive device dies;
singulating the plurality of passive device dies from the additional passive device die by applying a dicing process through a conductive via of the first RDLs; and
bonding a substrate to the first RDLs using one or more solder regions, wherein the first RDLs electrically connects the plurality of passive device dies to the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein bonding the substrate to the first RDLs comprises contacting the one or more solder regions to a conductive sidewall of the first RDLs.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first RDLs comprise:
a ground line in a first dielectric layer and having a sidewall coterminous with a first sidewall of the first molding compound; and
a power line in the first dielectric layer and having a sidewall coterminous with a second sidewall of the first molding compound, the second sidewall of the first molding compound being opposite the first sidewall of the first molding compound.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first RDLs comprise:
a ground line in a first dielectric layer; and
a power line in second dielectric layer different than the first dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1 further comprising forming a through via extending through the first molding compound and electrically connected to the one or more first RDLs.

### Claim 6 (depends on 5)

The method of claim 5, wherein singulating the plurality of passive device dies further comprises applying the dicing process to the through via.

### Claim 7 (depends on 1)

The method of claim 1 further comprising bonding an additional die to an opposing side of the first RDLs as the plurality of passive device dies.

### Claim 8 (depends on 1)

The method claim 1, wherein a first one of the plurality of passive device dies has a different height than a second one of the plurality of passive device dies.

### Claim 9

A package comprising:
a first die encapsulated in a first molding compound;
a second die encapsulated in a second molding compound, the first molding compound contacting the second molding compound;
a first conductive feature extending at least from a topmost portion of the first molding compound to a bottommost portion of the first molding compound, the first conductive feature is electrically connected to the first die by a first redistribution layer (RDL); and
a second conductive feature extending at least from a topmost portion of the second molding compound to the bottommost portion of the second molding compound, the first conductive feature is directly bonded to the second conductive feature, the second conductive feature is electrically connected to the second die by a second RDL, and wherein the first die and the second die are both disposed between the first RDL and the second RDL.

### Claim 10 (depends on 9)

The package of claim 9 further comprising a package substrate bonded to the first RDL by a solder region.

### Claim 11 (depends on 10)

The package of claim 10, wherein the solder region contacts the first conductive feature and the second conductive feature.

### Claim 12 (depends on 10)

The package of claim 10, wherein the solder region extends between first RDL and the package substrate along a line perpendicular to a major surface of the package substrate.

### Claim 13 (depends on 9)

The package of claim 9, wherein the first die and the second die are each substantially free of any active devices.

### Claim 14 (depends on 9)

The package of claim 9 further comprising a third die encapsulated in the first molding compound and a fourth die encapsulated in the second molding compound.

### Claim 15 (depends on 9)

The package of claim 9, wherein the first die is bonded to the first RDL by a solder region, and wherein the second die is bonded to the second RDL by a solder region.

### Claim 16

A package comprising:
a first passive device die;
a second passive device die;
a molding compound encapsulating the first passive device die and the second passive device die;
a conductive line electrically connecting the first passive device die to the second passive device die;
an input/output contact forming an interface with the conductive line; and
a solder region bonding the first passive device die and the second passive device die to a substrate, wherein the solder region extends along sidewalls of the conductive line and the input/output contact, and wherein the interface between the input/output contact and the conductive line extends to the solder region.

### Claim 17 (depends on 16)

The package of claim 16, wherein the input/output contact extends through the molding compound.

### Claim 18 (depends on 16)

The package of claim 16, wherein the molding compound forms an interface with the input/output contact opposite the interface between the input/output contact and the conductive line.

### Claim 19 (depends on 16)

The package of claim 16, wherein the conductive line is disposed between the substrate and the first passive device die.

### Claim 20 (depends on 16)

The package of claim 16, wherein the first passive device die is disposed between the conductive line and the substrate.