# US 10,504,751 B2 · Package structures and method of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,751 B2 - Document ID: US10504751B2 - Status: Granted - Kind: B2 - Application number: 16/041,904 - Filed: 2018-07-23 - Published: 2018-11-15 - Granted: 2019-12-10 - Earliest claimed: 2015-02-12 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Hsien-Wei Chen; Cheng-Hsien Hsieh; Li-Han Hsu; Lai Wei Chih - Web page: https://patentgrep.com/patent/US10504751B2 ## CPC - H10W 74/014: {using batch processing} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/0198: {batch processes} - H10W 72/073: {of die-attach connectors} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/874: {On different surfaces} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/722: {between stacked chips} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Package structures and methods of forming package structures are described. A method includes depositing and patterning a first dielectric material. The first dielectric material is deposited in first and second package component regions and in a scribe line region. The scribe line region is disposed between the first and second package component regions. The patterning the first dielectric material forms a first dielectric layer in each of the first and second package component regions and a dummy block in the scribe line region. The dummy block is separated from the first dielectric layer in each of the first and second package component regions. The method further includes forming a metallization pattern on the first dielectric layer; depositing a second dielectric material on the first dielectric layer and the metallization pattern; and patterning the second dielectric material to form a second dielectric layer. ## Claims ### Claim 1 A structure comprising: an integrated circuit die; an encapsulant at least laterally encapsulating the integrated circuit die; a first dielectric layer on a first side of the encapsulant and the integrated circuit die; a metallization pattern extending along and through the first dielectric layer, the metallization pattern being connected to the integrated circuit die; and a first dummy block portion on the first side of the encapsulant, the first dummy block portion being separated from the first dielectric layer by a separation region, a sidewall of the first dielectric layer and a sidewall of the first dummy block portion facing the separation region, a bottom of the separation region being level with a top surface of the encapsulant, a bottom surface of the first dummy block portion, and a bottom surface of the first dielectric layer. ### Claim 2 (depends on 1) The structure of claim 1, wherein the first dielectric layer and the first dummy block portion comprise a same dielectric material, and the first dielectric layer and the first dummy block portion extend from the first side of the encapsulant by a same distance. ### Claim 3 (depends on 1) The structure of claim 1 further comprising: a second dielectric layer on the metallization pattern; and a second dummy block portion on the first dummy block portion, the second dummy block portion being separated from the second dielectric layer by the separation region. ### Claim 4 (depends on 3) The structure of claim 3, wherein the second dummy block portion is co-extensive with the first dummy block portion in perpendicular directions within a plane parallel to an interface between the first dummy block portion and the second dummy block portion. ### Claim 5 (depends on 3) The structure of claim 3, wherein the second dummy block portion is co-extensive with the first dummy block portion in a first direction within a plane parallel to an interface between the first dummy block portion and the second dummy block portion, the second dummy block portion not being co-extensive with the first dummy block portion in a second direction within the plane, the second direction being perpendicular to the first direction. ### Claim 6 (depends on 3) The structure of claim 3, wherein the second dummy block portion is not co-extensive with the first dummy block portion in perpendicular directions within a plane parallel to an interface between the first dummy block portion and the second dummy block portion. ### Claim 7 (depends on 3) The structure of claim 3, wherein the second dummy block portion is one of a plurality of second dummy block portions on the first dummy block portion, the second dummy block portions being aligned in a first direction within a plane parallel to an interface between the first dummy block portion and the second dummy block portions, the first direction extending parallel to an edge of the integrated circuit die. ### Claim 8 (depends on 3) The structure of claim 3, wherein the second dummy block portion is one of a plurality of second dummy block portions on the first dummy block portion, the second dummy block portions being aligned in a first direction within a plane parallel to an interface between the first dummy block portion and the second dummy block portions, the first direction extending perpendicular to an edge of the integrated circuit die. ### Claim 9 (depends on 1) The structure of claim 1, wherein the first dummy block portion extends partially along an edge of the encapsulant. ### Claim 10 (depends on 1) The structure of claim 1, wherein the first dummy block portion extends continuously along a plurality of edges of the encapsulant. ### Claim 11 (depends on 1) The structure of claim 1, wherein the first dummy block portion is one of a plurality of first dummy block portions, each of the first dummy block portions extending partially along a same edge of the encapsulant. ### Claim 12 (depends on 1) The structure of claim 1, wherein the first dummy block portion is free from the metallization pattern. ### Claim 13 A structure comprising: an integrated circuit die; an encapsulant at least laterally encapsulating the integrated circuit die, the encapsulant having a first width; a through via extending through the encapsulant; and a redistribution structure connected to the through via and the encapsulant, the redistribution structure comprising: a first dielectric layer contacting a first side of the encapsulant and the integrated circuit die, the first dielectric layer having a second width, the second width being less than the first width; and a first dummy block portion contacting the first side of the encapsulant, the first dummy block portion being separated from the first dielectric layer by a separation region, the separation region being free from material of the first dielectric layer and material of the first dummy block portion, bottoms of the separation region, the first dummy block portion, and the first dielectric layer being planar with an interface between the first dummy block portion and the encapsulant. ### Claim 14 (depends on 13) The structure of claim 13, wherein a combined width of the first dielectric layer, the first dummy block portion, and the separation region equals the first width of the encapsulant. ### Claim 15 (depends on 13) The structure of claim 13, wherein the first dielectric layer and the first dummy block portion comprise a same dielectric material, and the first dielectric layer and the first dummy block portion extend from the first side of the encapsulant by a same distance. ### Claim 16 (depends on 13) The structure of claim 13 further comprising: a substrate; first external electrical connectors connecting the substrate to the redistribution structure; a package; and second external electrical connectors connecting the package to the through via. ### Claim 17 A structure comprising: a package region comprising: a die, an encapsulant at least laterally encapsulating the die, and a redistribution structure on a first side of the encapsulant and the die, the redistribution structure comprising a first dielectric layer, a second dielectric layer, and a metallization pattern between the first dielectric layer and the second dielectric layer, the metallization pattern being connected to the die; and a periphery region along an edge of the package region, the periphery region comprising a first dummy block portion on the first side of the encapsulant, the first dummy block portion being separated from the first dielectric layer and the second dielectric layer by an opening, wherein the first side of the encapsulant is a planar surface extending continuously across the package region and the periphery region. ### Claim 18 (depends on 17) The structure of claim 17, wherein the periphery region further comprises a second dummy block portion on the first dummy block portion, the first dummy block portion corresponding to the first dielectric layer relative to the encapsulant, the second dummy block portion corresponding to the second dielectric layer relative to the encapsulant. ### Claim 19 (depends on 17) The structure of claim 17, wherein the opening has a width in a range from 50 μm to 100 μm. ### Claim 20 (depends on 17) The structure of claim 17 further comprising a substrate attached to the redistribution structure by external electrical connectors.