# US 10,504,749 B2 · Semiconductor device

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- Number: US 10,504,749 B2
- Document ID: US10504749B2
- Status: Granted
- Kind: B2
- Application number: 16/070,893
- Filed: 2017-02-07
- Published: 2019-01-24
- Granted: 2019-12-10
- Earliest claimed: 2016-02-29
- Assignees: Mitsubishi Materials Corporation
- Applicants: Mitsubishi Materials Corporation
- Inventors: Shuji Nishimoto; Yoshiyuki Nagatomo
- Web page: https://patentgrep.com/patent/US10504749B2

## CPC

- H10W 72/071: {Connecting or disconnecting}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/098: {Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence)}
- H10W 72/015: {of bond wires}
- H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01336: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01351: {Changing the shapes of die-attach connectors}
- H10W 72/01361: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01351)}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01961: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951)}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07553: {changes in shapes}
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/531: {Shapes of wire connectors}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device of the present invention includes a circuit layer formed of a conductive material, a semiconductor element mounted on a first surface of the circuit layer, and a ceramic substrate disposed on a second surface of the circuit layer, in which a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer, and the Ag layer of the Ag underlayer and the semiconductor element are directly joined together.

## Claims

### Claim 1

A semiconductor device comprising:
a circuit layer formed of a conductive material;
a semiconductor element mounted on a first surface of the circuit layer; and
a ceramic substrate disposed on a second surface of the circuit layer,
wherein a Ag underlayer having a glass layer and a Ag layer laminated on the glass layer is formed on the first surface of the circuit layer,
the Ag layer of the Ag underlayer and the semiconductor element are directly joined together,
conductive particles made of crystalline particles containing at least one of Ag or Al are dispersed inside the glass layer, and
glass particles are dispersed inside the Ag layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein, on a surface of the semiconductor element which is joined to the Ag layer, any of a Au film formed of Au or a Au alloy and a Ag film formed of Ag or a Ag alloy is formed.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the semiconductor element is a power semiconductor element.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2,
wherein the semiconductor element is a power semiconductor element.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein, an average crystal grain diameter of the Ag layer in the Ag underlayer is in a range of 0.5 μm or more and 3.0 μm or less.