# US 10,504,747 B2 · Method of gap filling using conformal deposition-annealing-etching cycle for reducing seam void and bending

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- Number: US 10,504,747 B2
- Document ID: US10504747B2
- Status: Granted
- Kind: B2
- Application number: 15/720,087
- Filed: 2017-09-29
- Published: 2019-04-04
- Granted: 2019-12-10
- Earliest claimed: 2017-09-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: De-Wei Yu; Chien-Hao Chen; Chia-Ao Chang; Pin-Ju Liang
- Web page: https://patentgrep.com/patent/US10504747B2

## CPC

- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10P 50/242: {of Group IV materials}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2924: {Structures}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3238: {being insulating materials}
- H10P 36/00: Gettering within semiconductor bodies
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes depositing a silicon layer, which includes first portions over a plurality of strips, and second portions filled into trenches between the plurality of strips. The plurality of strips protrudes higher than a base structure. The method further includes performing an anneal to allow parts of the first portions of the silicon layer to migrate toward lower parts of the plurality of trenches, and performing an etching on the silicon layer to remove some portions of the silicon layer.

## Claims

### Claim 1

A method comprising:
depositing a first silicon layer, wherein the first silicon layer comprises first portions over a plurality of strips that protrudes higher than a base structure, and second portions filled into trenches between the plurality of strips;
performing a first anneal to allow parts of the first portions of the first silicon layer to migrate toward lower parts of the trenches; and
performing a first etching on the first silicon layer to remove some portions of the first silicon layer.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
depositing a second silicon layer on the first silicon layer;
performing a second anneal to anneal the first silicon layer and the second silicon layer; and
performing a second etching on the first silicon layer and the second silicon layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the plurality of strips comprises a plurality of dummy gate stacks, and the method further comprises:
forming a dielectric layer on the plurality of dummy gate stacks, with the first silicon layer being deposited on the dielectric layer; and
removing the first silicon layer and the second silicon layer.

### Claim 4 (depends on 3)

The method of claim 3 further comprising:
removing the plurality of dummy gate stacks to form recesses; and
forming replacement gates in the recesses, with the first silicon layer and the second silicon layer removed after the replacement gates are formed.

### Claim 5 (depends on 3)

The method of claim 3 further comprising removing the dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plurality of strips comprises a plurality of semiconductor fins, and the method further comprises forming a dummy gate dielectric layer on the plurality of semiconductor fins, with the first silicon layer being deposited on the dummy gate dielectric layer.

### Claim 7 (depends on 1)

The method of claim 1 further comprising patterning the first silicon layer to form a dummy gate stack.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first anneal is performed at a temperature between about 450° C. and about 600° C.

### Claim 9

A method comprising:
forming source/drain regions on a plurality of semiconductor fins, wherein the plurality of semiconductor fins is between a plurality of dummy gate stacks;
forming a dielectric layer on the source/drain regions and the plurality of dummy gate stacks;
fully filling trenches between the plurality of dummy gate stacks with a semiconductor material, wherein the fully filling the trenches comprises:
performing a first deposition-anneal-etching cycle to form a first semiconductor layer over the dielectric layer, with the first semiconductor layer partially filling trenches between the plurality of dummy gate stacks;
planarizing the semiconductor material, until the plurality of dummy gate stacks is exposed;
replacing the plurality of dummy gate stacks with replacement gates; and
removing remaining portions of the semiconductor material and the first semiconductor layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first deposition-anneal-etching cycle comprises:
depositing the first semiconductor layer as a conformal layer;
annealing the first semiconductor layer; and
etching the first semiconductor layer to remove some portions of the first semiconductor layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein in the annealing, upper portions of the first semiconductor layer migrate to lower parts of the trenches.

### Claim 12 (depends on 10)

The method of claim 10, wherein the annealing is performed at a temperature between about 450° C. and about 600° C.

### Claim 13 (depends on 10)

The method of claim 10, wherein the annealing results in a thickness of a top portion of the first semiconductor layer on top of one of the plurality of dummy gate stacks to be reduced by more than about 25 percent.

### Claim 14 (depends on 9)

The method of claim 9, wherein:
the fully filling the trenches with the semiconductor material further comprises performing a second deposition-anneal-etching cycle to form a second semiconductor layer over the first semiconductor layer.

### Claim 15

A method comprising:
performing a plurality of deposition-anneal-etch cycles to stack a plurality of semiconductor layers, with the plurality of semiconductor layers comprising first portions over a plurality of dummy gate stacks, and second portions partially filling trenches between the plurality of dummy gate stacks, and the plurality of dummy gate stacks protrude over isolation regions, wherein each of the plurality of deposition-anneal-etch cycles comprises:
depositing a conformal semiconductor layer;
performing an anneal on the conformal semiconductor layer to turn the conformal semiconductor layer into a non-conformal layer having a bottom-thick profile; and
performing an etching to partially remove the non-conformal layer; and
filling remaining portions of the trenches with an additional semiconductor layer.

### Claim 16 (depends on 15)

The method of claim 15 further comprising, performing a removal process to fully remove the plurality of semiconductor layers and the additional semiconductor layer.

### Claim 17 (depends on 16)

The method of claim 16 further comprising, before the removal process, replacing the plurality of dummy gate stacks with replacement gates.

### Claim 18 (depends on 16)

The method of claim 16 further comprising, after the removal process, forming an inter-layer dielectric into spaces left by the removed plurality of semiconductor layers and the removed additional semiconductor layer.

### Claim 19 (depends on 15)

The method of claim 15 further comprising performing a planarization on the plurality of semiconductor layers and the additional semiconductor layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein during the anneal, thicknesses of higher portions and lower portions of the plurality of semiconductor layers are changed.