# US 10,504,736 B2 · Plating interconnect for silicon chip

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- Number: US 10,504,736 B2
- Document ID: US10504736B2
- Status: Granted
- Kind: B2
- Application number: 14/870,773
- Filed: 2015-09-30
- Published: 2017-03-30
- Granted: 2019-12-10
- Earliest claimed: 2015-09-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Jerard Canuto Malado; Antonio Rosario Taloban, Jr.
- Web page: https://patentgrep.com/patent/US10504736B2

## CPC

- H10P 14/46: using a liquid
- H10P 14/412: {Deposition of metallic or metal-silicide materials}
- H10W 20/068: {by using a laser, e.g. laser cutting or laser direct writing}
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0711: {Apparatus therefor}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/874: {On different surfaces}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/00: Package configurations
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.

## Claims

### Claim 1

A silicon chip package comprising:
a front assembly having lead fingers, the lead fingers having a first end that is closest to the front assembly and a second end that is furthest from the front assembly;
a die attached on the front assembly;
a plastic pre-mold formed over the die and a portion of the first end of the lead fingers;
rigid traces formed into the plastic pre-mold, every portion of the rigid traces lying at or below a top surface of the plastic pre-mold, the rigid traces providing continuous interconnections between the die and the first end of the lead fingers; and
a mold formed over the rigid traces, the plastic pre-mold, and a portion of the first end of the lead fingers, the mold not contacting any portion of the second end of the lead fingers.

### Claim 2 (depends on 1)

The silicon chip package of claim 1, wherein trenches for the rigid traces are etched into the pre-mold by laser ablation.

### Claim 3 (depends on 1)

The silicon chip package of claim 1, wherein the first end of each lead finger is formed above a lower surface of the die, and wherein the second end of each lead finger is formed below the lower surface of the die.

### Claim 4 (depends on 1)

The silicon chip package of claim 1, wherein the die comprises bond pads that connect the rigid traces to the die.

### Claim 5 (depends on 1)

The silicon chip package of claim 1 further comprising a die pad wherein the die is mounted on the die pad.

### Claim 6 (depends on 1)

The silicon chip package of claim 1, wherein the silicon chip package is a quad flat package (QFP).

### Claim 7

A semiconductor die package comprising:
a die pad;
a semiconductor die attached to the die pad;
a plurality of lead fingers extending away from the die pad, each lead finger having a first end formed above the die pad and having a second end formed below the die pad;
a pre-mold material formed over the semiconductor die and a portion of the first end of each lead finger;
a plurality of rigid traces formed in the pre-mold material to connect the respective first end of each lead finger to the semiconductor die, every portion of the plurality of rigid traces lying at or below a top surface of the plastic pre-mold; and
a mold formed over the rigid traces, the pre-mold material, and a portion of the first end of the lead fingers, the mold not contacting any portion of the second end of each lead finger.

### Claim 8 (depends on 7)

The semiconductor die package of claim 7, wherein the rigid traces are formed in trenches in the pre-mold material formed by laser ablation.

### Claim 9 (depends on 7)

The semiconductor die package of claim 7, wherein the semiconductor die comprises silicon.

### Claim 10 (depends on 7)

The semiconductor die package of claim 7, wherein the die comprises bond pads that connect each respective rigid trace to the die.

### Claim 11 (depends on 7)

The semiconductor die package of claim 7, wherein each rigid trace of the plurality of rigid traces is formed in a respective trench of the pre-mold material.

### Claim 12 (depends on 11)

The semiconductor die package of claim 11, wherein each respective trench is etched in the pre-mold material.

### Claim 13 (depends on 7)

The semiconductor die package of claim 7, wherein the die package is a quad flat package (QFP).