# US 10,504,733 B2 · Etching platinum-containing thin film using protective cap layer

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- Number: US 10,504,733 B2
- Document ID: US10504733B2
- Status: Granted
- Kind: B2
- Application number: 15/714,169
- Filed: 2017-09-25
- Published: 2018-07-19
- Granted: 2019-12-10
- Earliest claimed: 2017-01-19
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sebastian Meier; Helmut Rinck; Mike Mittelstaedt
- Web page: https://patentgrep.com/patent/US10504733B2

## CPC

- H10D 30/0212: {using self-aligned silicidation}
- C01G 55/00: Compounds of ruthenium, rhodium, palladium, osmium, iridium, or platinum
- C01G 55/004: {Oxides; Hydroxides}
- H10D 1/474: {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 50/667: {by liquid etching only}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/0698: {Local interconnections}
- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10W 72/00: Interconnections or connectors in packages
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0174: {the gate conductors being silicided}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/075: {of bond wires}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C01G: COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F (metal hydrides {monoborane, diborane or addition complexes thereof} C01B6/00; salts of oxyacids of halogens C01B11/00; peroxides, salts or peroxyacids C01B15/00; thiosulfates, dithionites, polythionates C01B17/64; compounds containing selenium, or tellurium C01B19/00; binary compounds of nitrogen with metals C01B21/06; azides C01B21/08; {compounds containing nitrogen, other non-metals and metal C01B21/082}; metal amides C01B21/092; nitrites C01B21/50; {compounds of noble gases C01B23/0005}; phosphides C01B25/08; salts of oxyacids of phosphorus C01B25/16; carbides C01B32/90; compounds containing silicon C01B33/00; compounds containing boron C01B35/00; compounds having molecular sieve properties but not having base-exchange properties C01B37/00; compounds having molecular sieve and base-exchange properties, e.g. crystalline zeolites, C01B39/00; cyanides C01C3/08; salts of cyanamide C01C3/16; thiocyanates C01C3/20)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

## Claims

### Claim 1

A method of forming a microelectronic device, comprising:
providing a substrate having a top surface;
forming a platinum-containing layer on the top surface of the substrate, the platinum-containing layer having a bottom surface on the top surface of the substrate and having a top surface located opposite from and facing away from the top surface of the substrate;
forming a cap layer comprising one selected from a group consisting essentially of a cap layer that is primarily aluminum and a cap layer that is primarily copper on the top surface of the platinum-containing layer, wherein an interface between the cap layer and the platinum-containing layer at the top surface of the platinum-containing layer is free of platinum oxide; and
removing the cap layer and at least a portion of the platinum-containing layer by a wet etch process, a same wet etchant of the wet etch process removing both the cap layer and the platinum containing layer, the cap layer having an etch rate at least twice the etch rate of the platinum containing layer in the same wet etchant, the wet etch process exposing the top surface of the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the cap layer includes primarily aluminum.

### Claim 3 (depends on 1)

The method of claim 1, wherein the cap layer has a composition equal to a composition of a layer in an interconnect line of the microelectronic device.

### Claim 4 (depends on 1)

The method of claim 1, wherein the wet etch process uses aqua regia.

### Claim 5 (depends on 1)

The method of claim 1, wherein the cap layer is formed before the platinum-containing layer is exposed to an oxidizing ambient.

### Claim 6 (depends on 1)

The method of claim 1, wherein the cap layer is formed after removing platinum oxide from the top surface of the platinum-containing layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein removing the platinum oxide is performed using a sputter etch process.

### Claim 8 (depends on 6)

The method of claim 6, wherein removing the platinum oxide is performed by heating the platinum-containing layer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a hard mask over a portion of the platinum-containing layer prior to forming the cap layer, wherein the cap layer is formed over the hard mask.

### Claim 10 (depends on 9)

The method of claim 9, wherein the hard mask includes dielectric material.

### Claim 11 (depends on 9)

The method of claim 9, wherein the hard mask is electrically conductive.

### Claim 12 (depends on 11)

The method of claim 11, further comprising patterning the hard mask on a remaining portion of the platinum-containing layer after removing the cap layer and the at least a portion of the platinum-containing layer using the wet etch process.

### Claim 13 (depends on 1)

The method of claim 1, further comprising:
removing a portion of the cap layer over a corresponding portion of the platinum-containing layer; and
forming masking platinum oxide on the platinum-containing layer where exposed by the removing a portion of the cap layer, prior to removing the remaining cap layer and the portion of the platinum-containing layer using the wet etch process, wherein the masking platinum oxide blocks removal of the portion of the platinum-containing layer under the masking platinum oxide.

### Claim 14 (depends on 1)

The method of claim 1, wherein the platinum-containing layer contacts exposed silicon containing semiconductor material; and further comprising heating the platinum-containing layer to form platinum silicide, prior to removing the cap layer and the at least a portion of the platinum-containing layer.

### Claim 15 (depends on 1)

The method of claim 1, wherein at least a portion of the platinum containing layer provides a local interconnect.

### Claim 16 (depends on 1)

The method of claim 1, wherein the local interconnect makes an electrical connection to platinum silicide.

### Claim 17 (depends on 1)

The method of claim 1, wherein a least a portion of the platinum containing layer provides a bond pad.