# US 10,504,603 B2 · System-in-package module with memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,603 B2
- Document ID: US10504603B2
- Status: Granted
- Kind: B2
- Application number: 15/657,235
- Filed: 2017-07-24
- Published: 2017-11-09
- Granted: 2019-12-10
- Earliest claimed: 2013-10-23
- Assignees: Etron Technology, Inc.
- Applicants: Etron Technology, Inc.
- Inventors: Weng-Dah Ken; Chao-Chun Lu
- Web page: https://patentgrep.com/patent/US10504603B2

## CPC

- G11C 29/023: {in clock generator or timing circuitry}
- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- G06F 11/1064: {in cache or content addressable memories}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

## Claims

### Claim 1

A system-in-package (SIP) module with memory, the SIP module comprising:
a cache memory;
a memory controller;
a memory; and
a substrate, wherein the cache memory, the memory controller, and the memory are co-packaged over the substrate, and the cache memory and the memory controller are formed on a same semiconductor chip;
wherein the memory controller accesses the memory and the cache memory through a first reconfigurable bus, transmits data to an external circuit or receives data from the external circuit through a second reconfigurable bus, and the memory controller is capable of dynamically changing a first swing voltage and an address width of the first reconfigurable bus according to a stacked number corresponding to the memory and a bus width of the first reconfigurable bus, or a second swing voltage and an address width of the second reconfigurable bus according to the stacked number corresponding to the memory and a bus width of the second reconfigurable bus, or the first swing voltage and the address width of the first reconfigurable bus and the second swing voltage and the address width of the second reconfigurable bus according to the stacked number corresponding to the memory, the bus width of the first reconfigurable bus, and the bus width of the second reconfigurable bus.

### Claim 2 (depends on 1)

The SIP module of claim 1, wherein the cache memory, the memory controller, and the memory are installed on the substrate respectively, or are installed on the substrate after the cache memory, the memory controller, and the memory are stacked together.

### Claim 3 (depends on 2)

The SIP module of claim 2, wherein the same semiconductor chip is a Si Chip made according to a complementary metal-oxide-semiconductor (CMOS) process.

### Claim 4 (depends on 1)

The SIP module of claim 1, wherein the cache memory is a static random access memory (SRAM) or a dynamic random access memory (DRAM), and the memory is a DRAM, or a plurality of DRAMs stacked together, and an operation speed or a band width of the cache memory is greater than an operation speed or a band width of the memory.

### Claim 5 (depends on 1)

The SIP module of claim 1, wherein the memory controller is used for accessing data of the cache memory or the memory according to commands of the SIP module, correcting data errors stored in the cache memory or the memory, dynamically changing the bus width of the first reconfigurable bus, or dynamically changing the bus width, or a second operation frequency of the second reconfigurable bus.

### Claim 6 (depends on 1)

The SIP module of claim 1, wherein the memory is installed above the cache memory and is electrically connected to the cache memory through silicon vias (TSV).

### Claim 7

A system-in-package module with memory, the SIP module comprising:
a non-memory chip having a first portion and a second portion, wherein the non-memory chip comprises a plurality of first electrical contacts and a plurality of second electrical contacts, and the plurality of first electrical contacts and the plurality of second electrical contacts are installed on the first portion and the second portion of the non-memory chip, respectively;
a memory having a plurality of third electrical contacts installed on one side thereof;
a substrate having a plurality of fourth electrical contacts installed on one side thereof and a plurality of fifth electrical contacts installed on another side thereof; and
an additional memory covering the non-memory chip, the memory, and the substrate, wherein the additional memory, the memory, and the non-memory chip form a three-layer structure, the non-memory chip exists between the additional memory and the memory, and the additional memory is directly electrically connected to the substrate;
wherein the plurality of first electrical contacts are electrically connected to the plurality of third electrical contacts to make the memory be electrically connected to the non-memory chip, the plurality of second electrical contacts are electrically connected to the plurality of fourth electrical contacts to make the substrate be electrically connected to the non-memory chip, and the substrate and the memory are both electrically connected to the same side of the non-memory chip or electrically connected to different sides of the non-memory chip;
wherein there is no direct electrical connection between the memory and the substrate.

### Claim 8 (depends on 7)

The SIP module of claim 7, wherein materials of the plurality of first electrical contacts, the plurality of second electrical contacts, the plurality of third electrical contacts, the plurality of fourth electrical contacts, or the plurality of fifth electrical contacts comprise solder or copper.