# US 10,504,592 B2 · Systems, methods and devices for programming a multilevel resistive memory cell

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- Number: US 10,504,592 B2
- Document ID: US10504592B2
- Status: Granted
- Kind: B2
- Application number: 15/853,423
- Filed: 2017-12-22
- Published: 2018-05-10
- Granted: 2019-12-10
- Earliest claimed: 2012-08-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Paolo Fantini; Massimo Ferro
- Web page: https://patentgrep.com/patent/US10504592B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2213/15: Current-voltage curve
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.

## Claims

### Claim 1

A method, comprising:
applying one or more first reverse-biased electrical pulses to a memory cell;
programming the memory cell from a first programming state to a reset programming state based at least in part on applying the one or more first reverse-biased electrical pulses;
applying one or more second reverse-biased electrical pulses to the memory cell; and
programming the memory cell from the reset programming state to the first programming state based at least in part on applying the one or more second reverse-biased electrical pulses.

### Claim 2 (depends on 1)

The method of claim 1, wherein the one or more first reverse-biased electrical pulses ramp in a first sequence and the one or more second reverse-biased electrical pulses ramp in a second sequence that is different from the second sequence.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first sequence comprises a rising staircase sequence and the second sequence comprises a falling staircase sequence.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
modulating an edge of at least some of the one or more first reverse-biased electrical pulses,
wherein programming the memory cell from the reset programming state to the first programming state is based at least in part on the modulating.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
applying one or more forward-biased electrical pulses to the memory cell; and
programming the memory cell from the first programming state to the reset programming state based at least in part on applying the one or more forward-biased electrical pulses, wherein the one or more forward-biased electrical pulses ramp in a rising staircase sequence.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
modulating an edge of at least some of the one or more forward-biased electrical pulses,
wherein programming the memory cell from the first programming state to the reset programming state is based at least in part on the modulating.

### Claim 7 (depends on 1)

The method of claim 1, wherein applying the one or more first reverse-biased electrical pulses comprises:
applying a voltage across a storage component such that a current flows from a first electrode to a second electrode of the storage component.

### Claim 8

A method, comprising:
applying one or more first reverse-biased electrical pulses to a memory cell;
programming the memory cell from a first programming state to a reset programming state based at least in part on applying the one or more first reverse-biased electrical pulses;
applying one or more first forward-biased electrical pulses to the memory cell; and
programming the memory cell from the reset programming state to a set programming state based at least in part on applying the one or more first forward-biased electrical pulses, wherein the one or more first forward-biased electrical pulses sequentially ramp in a falling staircase sequence.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
applying one or more second forward-biased electrical pulses to the memory cell; and
programming the memory cell from the set programming state to the reset programming state based at least in part on applying the one or more second forward-biased electrical pulses, wherein the one or more second forward-biased electrical pulses ramp in a rising staircase sequence.

### Claim 10 (depends on 9)

The method of claim 9, wherein the memory cell comprises a chalcogenide material.

### Claim 11 (depends on 10)

The method of claim 10, wherein the set programming state comprises a crystalline state having a first threshold voltage characteristic, and wherein the reset programming state comprises an amorphous state having a second threshold voltage characteristic.

### Claim 12

A memory device, comprising:
a memory array comprising a plurality of memory cells; and
a control unit configured to:
program one or more memory cells of the plurality of memory cells from a first programming state to a reset programming state based at least in part on applying one or more first reverse-biased electrical pulses; and
program the one or more memory cells from the reset programming state to the first programming state based at least in part on applying one or more second reverse-biased electrical pulses.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the one or more first reverse-biased electrical pulses ramp in a first sequence and the one or more second reverse-biased electrical pulses ramp in a second sequence, and wherein the first sequence is different than the second sequence.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the first sequence comprises an increasing sequence and the second sequence comprises a decreasing sequence.

### Claim 15 (depends on 12)

The memory device of claim 12, the control unit configured to:
modulate an edge of at least some of the one or more first reverse-biased electrical pulses,
wherein programming the one or more memory cells from the reset programming state to the first programming state is based at least in part on the modulating.

### Claim 16 (depends on 12)

The memory device of claim 12, the control unit configured to:
program the one or more memory cells from the first programming state to the reset programming state based at least in part on applying one or more forward-biased electrical pulses, wherein the one or more forward-biased electrical pulses ramp in a rising staircase sequence.

### Claim 17 (depends on 16)

The memory device of claim 16, the control unit configured to:
modulate an edge of at least some of the one or more forward-biased electrical pulses,
wherein programming the one or more memory cells from the first programming state to the reset programming state is based at least in part on the modulating.

### Claim 18 (depends on 12)

The memory device of claim 12, wherein each memory cell of the one or more memory cells comprises a chalcogenide material.

### Claim 19

A memory device, comprising
a memory array comprising a plurality of memory cells; and
a control unit configured to:
program one or more memory cells of the plurality of memory cells from a first programming state to a reset programming state based at least in part on applying one or more first reverse-biased electrical pulses; and
program the one or more memory cells from the reset programming state to a set programming state based at least in part on applying one or more first forward-biased electrical pulses that sequentially ramp in a decreasing sequence to the one or more memory cells.

### Claim 20 (depends on 19)

The memory device of claim 19, the control unit configured to:
program the one or more memory cells from the set programming state to the reset programming state based at least in part on applying one or more second forward-biased electrical pulses that sequentially ramp in an increasing sequence to the one or more memory cells.