# US 10,504,587 B2 · Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,587 B2 - Document ID: US10504587B2 - Status: Granted - Kind: B2 - Application number: 15/848,948 - Filed: 2017-12-20 - Published: 2019-02-07 - Granted: 2019-12-10 - Earliest claimed: 2017-12-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Carmine Miccoli; Akira Goda - Web page: https://patentgrep.com/patent/US10504587B2 ## CPC - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/3422: {Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/50004: {of threshold voltage} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5635: {Erasing circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2029/0409: {Online test} - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2-15, the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2-15), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption. ## Claims ### Claim 1 A memory controller, comprising: memory controller logic to: receive a request to read data stored in a first memory cell of a multi-level non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline; perform a read operation on a second memory cell of the multi-level non-volatile memory array to determine if the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is operated with a second wordline that is adjacent to the first wordline, in response to the request; assign a disturbed condition to the first memory cell responsive to a determination that the second memory cell is at the first programming level; and read the data stored in the first memory cell, in response to the request, with a compensated sensing parameter responsive to the assignment of the disturbed condition to the first memory cell; and error-correcting code logic to determine that the first memory cell is in the disturbed condition when the second memory cell is programmed to the first programming level. ### Claim 2 (depends on 1) The memory controller of claim 1, wherein the first memory cell is read at a first threshold voltage in the disturbed condition and is read at a second threshold voltage in an undisturbed condition, wherein the first threshold voltage is higher than the second threshold voltage. ### Claim 3 (depends on 1) The memory controller of claim 1, wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein a threshold voltage distribution of an erased TLC programming level of the plurality of memory cells is at least 2-3 times wider than threshold voltage distributions of each of the 14 other programming levels. ### Claim 4 (depends on 1) The memory controller of claim 1, wherein the first programming level is adjacent to the erased programming level, wherein the first programming level is a QLC Level 1 programming level, wherein the erased programming level is a QLC Level 0 programming level. ### Claim 5 (depends on 1) The memory controller of claim 1, wherein the second memory cell is programmed to one of 8 TLC programming levels prior to the first memory cell being programmed to one of 16 QLC programming levels, wherein the first memory cell is programmed to one of 16 QLC programming levels prior to the second memory cell being programmed to one of 16 QLC programming levels. ### Claim 6 (depends on 1) The memory controller of claim 1, wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein the plurality of memory cells is programmed to one of 8 TLC programming levels in a first programming pass, prior to being programmed to one of 16 QLC programming levels in a second programming pass. ### Claim 7 (depends on 1) The memory controller of claim 1, wherein the compensated sensing parameter includes an increased wordline read voltage level, an adjusted sense current, or an adjusted bitline voltage level, to compensate for an increased threshold voltage from the disturbed condition of the first memory cell. ### Claim 8 A system, comprising: a display; a memory array having a plurality of memory cells; and a memory controller, comprising: memory controller logic to: receive a request to read data stored in a first memory cell of a non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline; perform a read operation on a second memory cell of the non-volatile memory array to determine if the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is operated with a second wordline that is adjacent to the first wordline, in response to the request; assign a disturbed condition to the first memory cell responsive to a determination that the second memory cell is at the first programming level; and read the data stored in the first memory cell, in response to the request, with a compensated sensing parameter responsive to the association of the first memory cell with the disturbed condition; and error-correcting code logic to determine that the first memory cell is in the disturbed condition when the second memory cell is programmed to the first programming level. ### Claim 9 (depends on 8) The system of claim 8, wherein the first memory cell is read at a first threshold voltage in the disturbed condition and is read at a second threshold voltage in an undisturbed condition, wherein the first threshold voltage is higher than the second threshold voltage. ### Claim 10 (depends on 8) The system of claim 8, wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein a threshold voltage distribution of an erased TLC programming level of the plurality of memory cells is at least 2-3 times wider than threshold voltage distributions of the 14 other programming levels. ### Claim 11 (depends on 8) The system of claim 8, wherein the first programming level is adjacent to the erased programming level, wherein the first programming level is a QLC Level 1 programming level, wherein the erased programming level is a QLC Level 0 programming level. ### Claim 12 (depends on 8) The system of claim 8, wherein the second memory cell is programmed to one of 8 TLC programming levels prior to the first memory cell being programmed to one of 16 QLC programming levels, wherein the first memory cell is programmed to one of 16 QLC programming levels prior to the second memory cell being programmed to one of 16 QLC programming levels. ### Claim 13 (depends on 8) The system of claim 8, wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein the plurality of memory cells is programmed to one of 8 TLC programming levels in a first programming pass, prior to being programmed to one of 16 QLC programming levels in a second programming pass. ### Claim 14 (depends on 8) The system of claim 8, wherein the compensated sensing parameter includes an increased wordline read voltage level, an adjusted sense current, or an adjusted bitline voltage level, to compensate for an increased threshold voltage from the disturbed condition of the first memory cell. ### Claim 15 A method, comprising: receiving a request to read data stored in a first memory cell of a non-volatile memory array, wherein the data includes at least 4 bits, wherein the first memory cell is in a first wordline; performing a read operation on a second memory cell of the non-volatile memory array, the second memory cell being adjacent to the first memory cell on a memory cell string, wherein the second memory cell is in a second wordline that is adjacent to the first wordline, in response to the request; determining whether the second memory cell is programmed to a first programming level that is between an erased programming level and at least 14 other programming levels; assigning a disturbed condition to the first memory cell, responsive to a determination that the second memory cell is at the first programming level; and reading the data stored in the first memory cell, in response to the request, with a compensated sensing parameter responsive to assignment of the disturbed condition to the first memory cell. ### Claim 16 (depends on 15) The method of claim 15, wherein the first memory cell is read at a first threshold voltage in the disturbed condition and is read at a second threshold voltage in an undisturbed condition, wherein the first threshold voltage is higher than the second threshold voltage. ### Claim 17 (depends on 15) The method of claim 15, wherein the first programming level is adjacent to the erased programming level, and the first programming level is a QLC Level 1 programming level, while the erased programming level is a QLC Level 0 programming level. ### Claim 18 (depends on 15) The method of claim 15, wherein the first memory cell and the second memory cell are two of a plurality of memory cells, wherein the plurality of memory cells is programmed to one of 8 TLC programming levels in a first programming pass, prior to being programmed to one of 16 QLC programming levels in a second programming pass. ### Claim 19 (depends on 15) The method of claim 15, wherein the compensated sensing parameter includes an increased wordline read voltage level, an adjusted sense current, or an adjusted bitline voltage level, to compensate for an increased threshold voltage from the disturbed condition of the first memory cell.