# US 10,504,579 B2 · Directed per bank refresh command > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,579 B2 - Document ID: US10504579B2 - Status: Granted - Kind: B2 - Application number: 16/211,216 - Filed: 2018-12-05 - Published: 2019-04-11 - Granted: 2019-12-10 - Earliest claimed: 2013-09-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Kuljit S. Bains - Web page: https://patentgrep.com/patent/US10504579B2 ## CPC - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a per bank refresh counter applicable to multiple banks in a group. The memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command. The memory device refreshes a row identified by a row address counter for a bank identified by the per bank refresh command. The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition. ## Claims ### Claim 1 An apparatus, comprising: first counter logic circuitry and second counter logic circuitry to manage refresh commands of a memory device, the first counter logic circuitry to increment a first counter value in response to an all bank refresh command being issued to the memory device, the second counter logic circuitry to increment a second counter value in response to a single bank refresh command being issued to the memory device, the second counter logic circuitry to reset the second counter value in response to the all bank refresh command being issued to the memory device, the first counter logic circuitry to increment the first counter value and the second counter logic circuitry to roll over the second counter value in response to a separate single bank refresh command being issued for each bank of the memory device while the first counter value remains at a same value. ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the first counter logic circuitry is to increment the first counter value and the second counter logic circuitry is to reset but not roll over the second counter value in response to an all bank refresh command being issued to the memory device before a separate single bank refresh command is issued for each bank of the memory device while the first counter value remains at a same value. ### Claim 3 (depends on 1) The apparatus of claim 1 where the first counter logic circuitry and the second counter logic circuitry are disposed on a memory device. ### Claim 4 (depends on 1) The apparatus of claim 1 further comprising third logic circuitry to issue memory access commands to banks of the memory device other than a bank that is refreshing in response to a single bank refresh command that was issued for the bank. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the second counter logic circuitry is to reset the second counter in response to a RESET command being issued to the memory device. ### Claim 6 (depends on 1) The apparatus of claim 1 wherein the apparatus is a computing system, comprising: one or more processing cores; and, a network interface. ### Claim 7 (depends on 1) The apparatus of claim 1 where the first counter logic circuitry and the second counter logic circuitry are disposed on a memory device and where the memory device is disposed on a DIMM. ### Claim 8 A computing system, comprising: a plurality of processing cores; a network interface; a memory; a memory controller coupled to the memory; and, first counter logic circuitry and second counter logic circuitry to manage refresh commands of a memory device, the first counter logic circuitry to increment a first counter value in response to an all bank refresh command being issued to the memory device, the second counter logic circuitry to increment a second counter value in response to a single bank refresh command being issued to the memory device, the second counter logic circuitry to reset the second counter value in response to the all bank refresh command being issued to the memory device, the first counter logic circuitry to increment the first counter value and the second counter logic circuitry to roll over the second counter value in response to a separate single bank refresh command being issued for each bank of the memory device while the first counter value remains at a same value. ### Claim 9 (depends on 8) The computing system of claim 8 wherein the first counter logic circuitry is to increment the first counter value and the second counter logic circuitry is to reset but not roll over the second counter value in response to an all bank refresh command being issued to the memory device before a separate single bank refresh command is issued for each bank of the memory device while the first counter value remains at a same value. ### Claim 10 (depends on 8) The computing system of claim 8 where the first counter logic circuitry and the second counter logic circuitry are disposed on a memory device. ### Claim 11 (depends on 8) The computing system of claim 8 further comprising third logic circuitry to issue memory access commands to banks of the memory device other than a bank that is refreshing in response to a single bank refresh command that was issued for the bank. ### Claim 12 (depends on 8) The computing system of claim 8 wherein the second counter logic circuitry is to reset the second counter in response to a RESET command being issued to the memory device. ### Claim 13 (depends on 8) The computing system of claim 8 wherein the apparatus is a computing system, comprising: one or more processing cores; and, a network interface. ### Claim 14 (depends on 8) The computing system of claim 8 where the first counter logic circuitry and the second counter logic circuitry are disposed on a memory device and where the memory device is disposed on a DIMM. ### Claim 15 A method, comprising: managing refresh commands of a memory device by performing the following with first counter logic circuitry and second counter logic circuitry: with the first counter logic circuitry, incrementing a first counter value in response to an all bank refresh command being issued to the memory device; with the second counter logic circuitry, incrementing a second counter value in response to a single bank refresh command being issued to the memory device and resetting the second counter value in response to the all bank refresh command being issued to the memory device; with the first counter logic circuitry, incrementing the first counter value and the second counter logic circuitry to roll over the second counter value in response to a separate single bank refresh command being issued for each bank of the memory device while the first counter value remains at a same value. ### Claim 16 (depends on 15) The method of claim 15 further comprising: with the first counter logic circuitry, incrementing the first counter value; with the second counter logic circuitry, resetting but not rolling over the second counter value in response to an all bank refresh command being issued to the memory device before a separate single bank refresh command is issued for each bank of the memory device while the first counter value remains at a same value. ### Claim 17 (depends on 15) The method of claim 15 where the first counter logic circuitry and the second counter logic circuitry are disposed on a memory device. ### Claim 18 (depends on 15) The method of claim 15 wherein the method further comprises, with third logic circuitry, issuing memory access commands to banks of the memory device other than a bank that is refreshing in response to a single bank refresh command that was issued for the bank. ### Claim 19 (depends on 15) The method of claim 15 wherein method further comprises, with the second counter logic circuitry, resetting the second counter in response to a RESET command being issued to the memory device. ### Claim 20 (depends on 15) The method of claim 15 wherein the first counter logic circuitry and the second counter logic circuitry are disposed on a memory device and where the memory device is disposed on a DIMM.