# US 10,504,578 B2 · Volatile memory device with automatic lower power state > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,578 B2 - Document ID: US10504578B2 - Status: Granted - Kind: B2 - Application number: 15/768,536 - Filed: 2015-10-25 - Published: 2018-10-18 - Granted: 2019-12-10 - Earliest claimed: 2015-10-25 - Assignees: Hewlett Packard Enterprise Development LP - Applicants: Hewlett Packard Enterprise Development LP - Inventors: Reza M Bacchus; Melvin K Benedict; Eric L Pope - Web page: https://patentgrep.com/patent/US10504578B2 ## CPC - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 5/144: {Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby} - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 2207/2227: Standby or low power modes - G11C 2211/4067: Refresh in standby or low power modes - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter. ## Claims ### Claim 1 A volatile memory device comprising: a memory array of volatile charge storage cells; a counter to track a time since the volatile memory device has received a read/write command; a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter; and a buffer to store a page from the memory array; input/output circuitry, wherein the control element is to automatically rewrite the page from the buffer to the memory array and deactivate the buffer when automatically actuating the volatile memory device to the lower power state based on the time tracked by the counter. ### Claim 2 (depends on 1) The volatile memory device of claim 1 further comprising an external clock interface, wherein the control element is to automatically deactivate the external clock interface when automatically actuating the volatile memory device to the lower power state based on the time tracked by the counter. ### Claim 3 (depends on 1) The volatile memory device of claim 1 further comprising a refresh counter for a subset of the volatile charge storage cells, the refresh counter to track a time since a last refresh of the subset of the volatile charge storage cells, wherein the control element is to automatically deactivate the refresh counter when automatically actuating the volatile memory device to the lower power state based on the time tracked by the counter. ### Claim 4 (depends on 1) The volatile memory device of claim 1, wherein the control element is to (A) compare the counter signal to a first threshold and automatically change the volatile memory device to the lower power state in response to time tracked by the counter satisfying the first threshold and (B) is to compare the counter signal to a second threshold and automatically change the volatile memory device to a second lower power state, different than the first lower power state, in response to the time tracked by the counter satisfying the second threshold. ### Claim 5 (depends on 1) The volatile memory device of claim 1 further comprising an external clock interface, wherein the control element is to automatically deactivate the external clock interface when automatically actuating the volatile memory device to the second lower power state in response to the time tracked by the counter satisfying the second threshold. ### Claim 6 (depends on 1) The volatile memory device of claim 1, wherein the control element is to compare the counter signal to a third threshold and automatically change the volatile memory device to a third lower power state, different than the first lower power state and the second lower power state, in response to the time tracked by the counter satisfying the third threshold. ### Claim 7 (depends on 1) The volatile memory device of claim 1, wherein the control element is to automatically exit the lower power state in response to receiving a read/write command. ### Claim 8 (depends on 1) The volatile memory device of claim 1, wherein the changing of the volatile memories device to a lower power state is based upon a comparison of the time tracked by the counter to a threshold and wherein the threshold is dynamically adjustable. ### Claim 9 A storage system comprising: a memory controller; a volatile memory device; a data bus connecting the memory controller and the memory device; and a command/address bus connecting the memory controller in the memory device, wherein the volatile memory device comprises: a memory array of volatile charge storage cells; a counter to track a time since the volatile memory device has received a read/write command; a control element to automatically change the volatile memory device to a lower power state based on a signal from the counter and a buffer to store a page from the memory array; input/output circuitry, wherein the control element is to automatically rewrite the page from the buffer to the memory array and deactivate the buffer when automatically actuating the volatile memory device to the lower power state based on the time tracked by the counter. ### Claim 10 (depends on 9) The storage system of claim 9, wherein the volatile memory device comprises a dynamic random access type of memory. ### Claim 11 (depends on 9) The storage system of claim 9, further comprising an external clock interface, wherein the control element is to automatically deactivate the external clock interface when automatically actuating the volatile memory device to the lower power state based on the time tracked by the counter. ### Claim 12 (depends on 9) The storage system of claim 9, further comprising a refresh counter for a subset of the volatile charge storage cells, the refresh counter to track a time since a last refresh of the subset of the volatile charge storage cells, wherein the control element is to automatically deactivate the refresh counter when automatically actuating the volatile memory device to the lower power state based on the time tracked by the counter.