# US 10,504,573 B2 · Array of programmable memory elements with an array of second circuit elements > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,573 B2 - Document ID: US10504573B2 - Status: Granted - Kind: B2 - Application number: 15/762,752 - Filed: 2016-10-14 - Published: 2018-09-20 - Granted: 2019-12-10 - Earliest claimed: 2015-10-20 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: James Edward Myers; David William Howard; John Philip Biggs - Web page: https://patentgrep.com/patent/US10504573B2 ## CPC - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 14/0054: {in which the volatile element is a SRAM cell} - G11C 17/14: in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM - G11C 11/40: using transistors - G11C 17/12: using field-effect devices - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states; a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array. ## Claims ### Claim 1 A circuit comprising: an array of programmable memory elements fabricated on a substrate, each programmable memory element having one or more print-programmable regions which, when processed by an external print programming process in which a material is applied to at least partially cover one or more of the regions, are configured to program that programmable memory element to one of multiple states; a first set of control lines connected to the array of programmable memory elements, by which the contents of each individual programmable memory element are configured to be accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different from the programmable memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different from the first set of control lines, so as to provide access to second circuit elements in the array; wherein the second circuit elements are interleaved with the programmable memory elements on the substrate and the second circuit elements on the substrate are fabricated underneath the print-programmable regions so as to be at least partially overlapped by the print-programmable regions of the programmable memory elements. ### Claim 2 (depends on 1) The circuit according to claim 1, in which second circuit elements are disposed between programmable memory elements on the substrate. ### Claim 3 (depends on 1) The circuit according to claim 1, in which the regions comprise a pair of conductors which can be connected to one another by application of a conductive material onto the pair of conductors. ### Claim 4 (depends on 3) The circuit according to claim 3, comprising one or more components connected to each of the pair of conductors to provide an electrostatic discharge path. ### Claim 5 (depends on 1) The circuit according to claim 1, in which the programmable memory elements are read only memory (ROM) elements. ### Claim 6 (depends on 1) The circuit according to claim 1, in which the second circuit elements are random access memory (RAM) elements. ### Claim 7 (depends on 1) The circuit according to claim 1, in which the second circuit elements are: read only memory elements different from the programmable memory elements, light emitting elements or light sensing elements. ### Claim 8 (depends on 1) The circuit according to claim 1, in which: the first set of control lines comprises a first array of bit lines and a first array of word lines connected to the array of programmable memory elements, by which a word line of the first array of word lines enables access to a group of the programmable memory elements, the contents of individual programmable memory elements in a group of the programmable memory elements to which access has been enabled by said word line of the first array of word lines being configured to be accessed by the bit lines of the first array of bit lines; and the array of second circuit elements are connected to one but not the other of the first array of word lines and the first array of bit lines so as to provide access to second circuit elements in the array. ### Claim 9 (depends on 8) The circuit according to claim 8, in which the second set of control lines comprises a second array of word lines, by which a word line of the second array of word lines enables access to a group of the second circuit elements, individual second circuit elements in a group of the second circuit elements to which access has been enabled by said word line of the second array of word lines being configured to be accessed by the bit lines of the first array of bit lines. ### Claim 10 (depends on 8) The circuit according to claim 8, in which: the programmable memory elements are each connected to a single respective bit line, the circuit comprising memory reading circuitry configured to detect the state of a programmable memory element using the single respective bit line. ### Claim 11 (depends on 9) The circuit according to claim 9, in which each second circuit element is interleaved with multiple adjacent programmable memory elements on the substrate. ### Claim 12 (depends on 11) The circuit according to claim 11, in which: the second circuit elements are each connected to a pair of bit lines, the circuit comprising second circuit element access circuitry configured to access the state of a second circuit element according to a differential signal on the respective pair of bit lines. ### Claim 13 (depends on 12) The circuit according to claim 12, comprising: control circuitry to access the programmable memory elements in groups of n programmable memory elements, where n is an integer greater than 1; the control circuitry being configured to access the second circuit elements in groups of n second circuit elements, the circuit comprising two arrays of programmable memory elements in which in each array a group of n programmable memory elements is accessed by a respective control line of the first set of control lines, the control circuitry being configured to access second circuit elements in each of the two arrays in order to access a group of n second circuit elements. ### Claim 14 A circuit comprising: an array of first means for storing fabricated on a substrate, each first means for storing having one or more print-programmable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the print-programmable regions, are configured to program that first means for storing to one of multiple states; a first set of control lines connected to the array of first means for storing, by which the contents of each individual first means for storing are configured to be accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second means for storing, different from the first means for storing, each second means for storing connected to a control line of the first set of control lines and to another control line of a second set of control lines, different from the first set of control lines, so as to provide access to the second means for storing, wherein the second means for storing are interleaved with the first means for storing on the substrate and the second means for storing on the substrate are fabricated underneath the print-programmable regions so as to be at least partially overlapped by the print-programmable regions of the first means for storing. ### Claim 15 (depends on 1) A data processing apparatus comprising a substrate on which is fabricated a circuit according to claim 1 and processing circuitry configured to operate in accordance with information stored by the array of programmable memory elements. ### Claim 16 A method of fabricating a circuit comprising: fabricating an array of programmable-memory elements on a substrate, each programmable memory element having one or more print-programmable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the print-programming regions, are configured to program that programmable memory element to one of multiple states; fabricating a first set of control lines connected to the array of programmable memory elements, by which the contents of each individual programmable memory element are configured to be accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and fabricating an array of second circuit elements, different from the programmable memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different from the first set of control lines, so as to provide access to second circuit elements in the array; wherein the step of fabricating the array of second circuit elements comprises interleaving the array of second circuit elements with the programmable memory elements on the substrate and the second circuit elements on the substrate are fabricated underneath the print-programmable regions so as to be at least partially overlapped by the print-programmable regions of the programmable memory elements. ### Claim 17 (depends on 16) The method according to claim 16, comprising: processing one or more of the regions by the external non-electrical process by applying a conductive material over one or more of the regions using an ink-jet printing process.