# US 10,504,572 B2 · Methods for addressing high capacity SDRAM-like memory without increasing pin cost

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- Number: US 10,504,572 B2
- Document ID: US10504572B2
- Status: Granted
- Kind: B2
- Application number: 15/811,576
- Filed: 2017-11-13
- Published: 2018-04-12
- Granted: 2019-12-10
- Earliest claimed: 2016-03-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mu-Tien Chang; Dimin Niu; Hongzhong Zheng; Sun Young Lim; Indong Kim; Jangseok Choi
- Web page: https://patentgrep.com/patent/US10504572B2

## CPC

- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 7/1018: {Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters}
- G11C 8/04: using a sequential addressing device, e.g. shift register, counter
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

## Claims

### Claim 1

A method for addressing data in a memory device, the data being arranged in an array of rows and columns respectively indexed by a first number of row address bits and a second number of column address bits, the data being addressed using an architecture defined by a row address command specifying a third number of row address bits and a column address command specifying a fourth number of column address bits, the first number being greater than the third number, the method comprising:
splitting the first number of row address bits into a first subset of row address bits and a second subset of row address bits;
specifying the first subset in the row address command and the second subset in a next address command; and
processing the row address command as all or part of a row access command for accessing a row of the memory device.

### Claim 2 (depends on 1)

The method of claim 1, wherein the next address command is a column address command.

### Claim 3 (depends on 2)

The method of claim 2, further comprising processing the column address command immediately after the processing of the row address command.

### Claim 4 (depends on 1)

The method of claim 1, further comprising issuing the next address command after the row address command and before the column address command.

### Claim 5 (depends on 4)

The method of claim 4, wherein the issuing of the next address command immediately follows the issuing of the row address command.

### Claim 6 (depends on 1)

The method of claim 1, wherein the data is further arranged in subarrays of the rows and the columns, each of the subarrays being a subset of the array and being respectively indexed by the third number of row address bits and the second number of column address bits, the first subset of row address bits being the third number of row address bits,
wherein the memory device comprises a row buffer for each of the subarrays, and
wherein the method further comprises, for each of the subarrays, loading a corresponding said row buffer with row data from the subarray as specified by a corresponding said first subset of row address bits in response to the row address command.

### Claim 7 (depends on 6)

The method of claim 6, further comprising selecting one of the subarrays as specified by the second subset of row address bits in the next address command.

### Claim 8

A method for addressing data in a memory device, the data being arranged in an array of rows and columns respectively indexed by a first number of row address bits and a second number of column address bits, the data being addressed using an architecture defined by a row address command specifying a third number of row address bits followed by a column address command specifying a fourth number of column address bits, the second number being greater than the fourth number, the method comprising:
splitting the second number of column address bits into a third subset of column address bits and a fourth subset of column address bits;
specifying the fourth subset in the column address command and the third subset in a previous address command when the second number is greater than the fourth number; and
processing the column address command as all or part of a column access command corresponding to a row.

### Claim 9 (depends on 8)

The method of claim 8, wherein the previous address command is the row address command.

### Claim 10 (depends on 9)

The method of claim 9, further comprising processing the row address command immediately before the processing of the column address command.

### Claim 11 (depends on 9)

The method of claim 9, wherein the data is further arranged in subarrays of the rows and columns, each of the subarrays being a subset of the rows and columns and respectively indexed by the first number of row address bits and the fourth number of column address bits, the fourth subset of column address bits being the fourth number of column address bits,
wherein the memory device comprises a row buffer for each of the subarrays, and
wherein the method further comprises, for each subarray of the subarrays, loading a corresponding said row buffer with row data from the subarray as specified by the first number of row address bits in response to the row address command.

### Claim 12 (depends on 11)

The method of claim 11, further comprising selecting one of the subarrays as specified by the third subset of column address bits in the previous address command.

### Claim 13

A memory device comprising:
storage cells for storing data arranged in an array of rows and columns respectively indexed by a first number of row address bits and a second number of column address bits,
wherein the data in the memory device is addressed using an architecture defined by a row address command specifying a third number of row address bits followed by a column address command specifying a fourth number of column address bits, the first number being greater than the third number, and
wherein the memory device is configured to address the data by:
splitting the first number of row address bits into a first subset of row address bits and a second subset of row address bits, and specifying the first subset in the row address command and the second subset in a next address command when the first number is greater than the third number; and
processing the row address command as all or part of a row access of a row of the memory device.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the next address command is a column address command.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein the memory device is further configured to address the data by processing the column address command immediately after processing the row address command.

### Claim 16 (depends on 13)

The memory device of claim 13, wherein the addressing of the data further comprises processing the next address command after the row address command and before the column address command.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein the processing of the next address command immediately follows the processing of the row address command.

### Claim 18 (depends on 13)

The memory device of claim 13, wherein the data is further arranged in subarrays of the rows and columns, each of the subarrays being a subset of the rows and columns and respectively indexed by the third number of row address bits and the second number of column address bits, the first subset of row address bits being the third number of row address bits,
wherein the memory device further comprises a row buffer for each of the subarrays, and
wherein the addressing of the data further comprises, for each subarray of the subarrays, loading a corresponding said row buffer with row data from the subarray as specified by a corresponding said first subset of row address bits in response to the row address command.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein the addressing of the data further comprises selecting one of the subarrays as specified by the second subset of row address bits in the next address command.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the second number is greater than the fourth number,
wherein the data is further arranged in subarrays of the rows and columns, each of the subarrays being a subset of the rows and columns and respectively indexed by the first number of row address bits and the fourth number of column address bits,
wherein the memory device further comprises a row buffer for each of the subarrays, and
wherein the addressing of the data further comprises, for each of the subarrays, loading a corresponding said row buffer with row data from the subarray as specified by the first number of row address bits in response to the row address command, and selecting one of the subarrays as specified by a third subset of column address bits in a previous address command.