# US 10,504,571 B1 · Apparatus with a calibration mechanism

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,504,571 B1
- Document ID: US10504571B1
- Status: Granted
- Kind: B1
- Application number: 16/151,604
- Filed: 2018-10-04
- Granted: 2019-12-10
- Earliest claimed: 2018-10-04
- Assignees: Microa Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jason M. Johnson; Jung-Hwa Choi
- Web page: https://patentgrep.com/patent/US10504571B1

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 29/022: {in I/O circuitry}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/109: {Control signal input circuits}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50008: {of impedance}
- G11C 29/50012: {of timing}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 2207/105: Aspects related to pads, pins or terminals
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus includes: a ZQ connection configured to provide a reference resistance level for a ZQ calibration process that tunes one or more resistance levels associated with input/output signals at a corresponding one of a plurality of dies; one or more slave dies that are configured to implement the ZQ calibration process or a portion thereof; a master die configured to implement the ZQ calibration process or a portion thereof; and a calibration channel configured to communicate signals between the master die and the one or more of the slave dies for coordinating access to the ZQ connection across the connected dies in implementing the ZQ calibration process, wherein the plurality of dies includes the master die and the one or more slave dies.

## Claims

### Claim 1

An apparatus, comprising:
a ZQ pad configured to provide a reference resistance level for a ZQ calibration process that tunes one or more resistance levels associated with input/output signals at a corresponding one of a plurality of dies;
one or more slave dies electrically coupled to the ZQ pad, each of the slave dies configured to implement the ZQ calibration process or a portion thereof, wherein the plurality of dies includes the one or more slave dies;
a master die electrically coupled to the ZQ pad, the master die configured to implement the ZQ calibration process or a portion thereof, wherein the plurality of dies includes the master die; and
a calibration channel electrically coupling the master die and the slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the connected dies in implementing the ZQ calibration process.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the calibration channel includes a clock connection configured to communicate a calibration clock between the master die and the one or more slave dies, wherein the calibration clock is configured to coordinate timings associated with implementing the ZQ calibration process.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the master die is configured to transmit the calibration clock to the slave dies through the clock connection, wherein the calibration clock is a common clock signal across the master die and the slave dies used to coordinate each die to exclusively access the ZQ pad.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein each of the slave dies is configured to wait a unique number of clock cycles before implementing the ZQ calibration process or a portion thereof, wherein the unique number of clock cycles is relative to the implement the ZQ calibration process or a portion thereof at the master die.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the calibration channel includes an enable connection configured to communicate a calibration enable between the master die and the one or more slave dies, wherein the calibration enable is configured to enable the ZQ calibration process across the master die, one or more of the slave dies, or a combination thereof.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the master die is configured to transmit the calibration enable to the slave dies through the enable connection, wherein the calibration enable is a common enable signal across the master die and the slave dies.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the master die is configured to control a timing of the calibration enable to generate either a background calibration start or a command calibration start.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the calibration channel is configured to communicate signals in one direction from the master die to the slave dies.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the memory device comprises a dynamic random-access memory (DRAM).

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the DRAM is configured according to a Low Power 5 (LP5) specification, a double data rate (DDR) specification, or a combination thereof.