# US 10,504,568 B2 · Integrated circuit memory devices with customizable standard cell logic > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,568 B2 - Document ID: US10504568B2 - Status: Granted - Kind: B2 - Application number: 16/193,527 - Filed: 2018-11-16 - Published: 2019-03-21 - Granted: 2019-12-10 - Earliest claimed: 2015-11-09 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jin-Hyun Kim; Won-Hyung Song - Web page: https://patentgrep.com/patent/US10504568B2 ## CPC - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G06F 13/1668: {Details of memory controller} - G06F 13/4068: {Electrical coupling} - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a memory cell array; a standard cell region in which first type standard cells implemented to perform a first operation for accessing the memory cell array and second type standard cells performing the first operation and having performance characteristics different from performance characteristics of the first type standard cells are arranged; and a ROM including a program that performs place and route for the standard cells arranged in the standard cell region. ## Claims ### Claim 1 An integrated circuit device, comprising: a memory cell array in a semiconductor substrate; and user-programmable standard cell logic electrically coupled to said memory cell array, said user-programmable standard cell logic comprising a first plurality of standard cells configured to support first write and/or first read operations in said memory cell array, which are selected based on a first program state of said user-programmable standard cell logic, and a second plurality of standard cells configured to support second write and/or second read operations in said memory cell array, which are selected based on a second program state of said user-programmable standard cell logic, said second write and/or second read operations having different performance characteristics relative to performance characteristics associated with the first write and/or first read operations. ### Claim 2 (depends on 1) The device of claim 1, wherein the first plurality of standard cells have at least different latency characteristics relative to the second plurality of standard cells. ### Claim 3 (depends on 1) The device of claim 1, wherein the first plurality of standard cells have at least different operating speed characteristics relative to the second plurality of standard cells. ### Claim 4 (depends on 1) The device of claim 1, wherein the first plurality of standard cells have at least different power consumption characteristics relative to the second plurality of standard cells. ### Claim 5 (depends on 1) The device of claim 1, wherein the first plurality of standard cells have different latency, operating speed and power consumption requirements relative to the second plurality of standard cells. ### Claim 6 An integrated circuit device, comprising: a memory cell array in a semiconductor substrate; standard cell logic electrically coupled to said memory cell array, said standard cell logic comprising a first plurality of standard cells configured to support first write and/or first read operations in said memory cell array and a second plurality of standard cells configured to support second write and/or second read operations in said memory cell array having different performance characteristics relative to performance characteristics associated with the first write and/or first read operations; a programmable read-only memory (PROM) electrically coupled to said standard cell logic; input/output (I/O) pins; and first I/O standard cells in said standard cell logic, said first I/O standard cells configured to establish a first number of the I/O pins as active and a second number of the I/O pins as inactive, in accordance with I/O pin programming information contained in said PROM. ### Claim 7 (depends on 6) The device of claim 6, wherein the first number is selected from a group consisting of 8, 16 and 32 and the second number is selected from a group consisting of 0, 16 and 24. ### Claim 8 (depends on 6) The device of claim 6, wherein said memory cell array comprises a plurality of memory banks; and wherein said standard cell logic comprises a memory bank standard cell logic configured to set a number of active memory banks in the plurality of memory banks, in response to programming information contained in said PROM. ### Claim 9 An integrated circuit device, comprising: a memory cell array in a semiconductor substrate having input/output pin cells thereon; a programmable read-only memory (PROM) in the semiconductor substrate; and standard cell logic electrically coupled to said memory cell array and said PROM, said standard cell logic comprising I/O standard cells, which are configured to establish a first number of said I/O pin cells as active and a second number of the I/O pin cells as inactive, in accordance with I/O pad programming information contained in said PROM. ### Claim 10 (depends on 9) The device of claim 9, wherein the first number is selected from a group consisting of 8, 16 and 32 and the second number is selected from a group consisting of 0, 16 and 24.