# US 10,504,567 B2 · Sense amplifier with offset compensation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,567 B2 - Document ID: US10504567B2 - Status: Granted - Kind: B2 - Application number: 16/263,184 - Filed: 2019-01-31 - Published: 2019-05-30 - Granted: 2019-12-10 - Earliest claimed: 2015-08-25 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Robert Antonio Glazewski; Stephen Keith Heinrich-Barna; Saim Ahmad Qidwai - Web page: https://patentgrep.com/patent/US10504567B2 ## CPC - G11C 7/065: {Differential amplifiers of latching type} - G11C 11/221: {using ferroelectric capacitors} - G11C 11/2273: {Reading or sensing circuits or methods} - H03F 1/0205: {in transistor amplifiers} - H03F 3/16: with field-effect devices - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 11/223: {using MOS with ferroelectric gate insulating film} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03F: AMPLIFIERS ## Abstract An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously. ## Claims ### Claim 1 An integrated circuit device comprising: an sense amplifier having first and second input terminals; a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier; and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously. ### Claim 2 (depends on 1) The integrated circuit device of claim 1, wherein the first compensation circuit includes a first capacitor coupled in series with a first transistor, and wherein the second compensation circuit includes a second capacitor coupled in series with a second transistor. ### Claim 3 (depends on 1) The integrated circuit device of claim 1, wherein the first compensation circuit includes a first plurality of capacitors each having a substantially same capacitance value, and wherein the second compensation circuit includes a second plurality of capacitors having a substantially same capacitance value. ### Claim 4 (depends on 1) The integrated circuit device of claim 1, wherein the first compensation circuit includes a first plurality of capacitors having binary weighted capacitance values, and wherein the second compensation circuit includes a second plurality of capacitors having the binary weighted capacitance values. ### Claim 5 (depends on 1) The integrated circuit device of claim 1, wherein the latch circuit is operable to provide a first control signal to the first compensation circuit and to provide a second control signal to the second compensation circuit. ### Claim 6 (depends on 5) The integrated circuit device of claim 5, wherein the first compensation circuit includes a first capacitor having a first capacitance value coupled in series with a first transistor that includes a gate terminal to receive the first control signal, and wherein the second compensation circuit includes a second capacitor having a second capacitance value coupled in series with a second transistor having a gate terminal to receive the second control signal. ### Claim 7 (depends on 6) The integrated circuit device of claim 6, wherein the first and second transistors are of the same conductivity type. ### Claim 8 (depends on 7) The integrated circuit device of claim 7, wherein the first and second transistors are both n-channel metal-oxide semiconductor (NMOS) transistors. ### Claim 9 (depends on 7) The integrated circuit device of claim 7, wherein the first and second control signals are complementary signals with respect to each other. ### Claim 10 (depends on 9) The integrated circuit device of claim 9, wherein the latch circuit is operable to provide a third control signal and a fourth control signal, and wherein the compensation network includes: a third compensation circuit coupled to the first input terminal of the sense amplifier and including a third capacitor having a third capacitance value coupled in series with a third transistor that includes a gate terminal to receive the third control signal; and a fourth compensation circuit coupled to the second input terminal of the sense amplifier and including a fourth capacitor having a fourth capacitance value coupled in series with a fourth transistor that includes a gate terminal to receive the fourth control signal; wherein the third and fourth transistors are of the same conductivity type and the third and fourth control signals are complementary signals with respect to each other. ### Claim 11 (depends on 10) The integrated circuit device of claim 10, wherein the first, second, third and fourth transistors are of the same conductivity type. ### Claim 12 (depends on 10) The integrated circuit device of claim 10, wherein the latch circuit is operable to selectively enable either one of the third and fourth compensation circuits, but not both of the third and fourth compensation circuits simultaneously. ### Claim 13 (depends on 10) The integrated circuit device of claim 10, wherein: the first and third capacitance values are different capacitance values; the second and fourth capacitance values are different capacitance values; the first and third transistors are separately controllable to enable adding of one or both of the first and third capacitance values to the first input terminal; and the second and fourth transistors are separately controllable to enable adding of one or both of the second and fourth capacitance values to the second input terminal. ### Claim 14 (depends on 10) The integrated circuit device of claim 10, wherein: the first and third capacitance value are equal; the second and fourth capacitance values are equal; the first and third transistors are separately controllable to enable adding of one or both of the first and third capacitance values to the first input terminal; and the second and fourth transistors are separately controllable to enable adding of one or both of the second and fourth capacitance values to the second input terminal. ### Claim 15 (depends on 1) The integrated circuit device of claim 1, wherein the latch circuit includes a plurality of electronic fuse circuits or a plurality of electronic antifuse circuits. ### Claim 16 A system comprising: a processor; an input device coupled to the processor; an output device coupled to the processor; a memory array coupled to the processor; and a sense amplifier of the memory array, the sense amplifier comprising: a compensation network including a first compensation circuit coupled to a first input terminal of the sense amplifier and a second compensation circuit coupled to a second input terminal of the sense amplifier; and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously. ### Claim 17 (depends on 16) The system of claim 16, wherein the first compensation circuit includes a first capacitor coupled in series with a first transistor, wherein the second compensation circuit includes a second capacitor coupled in series with a second transistor, and wherein the latch circuit is operable to provide a first control signal to the first compensation circuit via a gate terminal of the first transistor and to provide a second control signal to the second compensation circuit via a gate terminal of the second transistor. ### Claim 18 (depends on 17) The system of claim 17, wherein: the compensation network includes: a third compensation circuit having a third capacitor coupled in series with a third transistor; and a fourth compensation circuit having a fourth capacitor coupled in series with a fourth transistor; and wherein the latch circuit is operable to provide a third control signal to the third compensation circuit via a gate terminal of the third transistor and to provide a fourth control signal to the fourth compensation circuit via a gate terminal of the fourth transistor. ### Claim 19 (depends on 16) The system of claim 16, wherein the memory array includes ferroelectric memory cells.