# US 10,504,565 B2 · Power management integrated circuit with dual power feed > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,565 B2 - Document ID: US10504565B2 - Status: Granted - Kind: B2 - Application number: 16/438,311 - Filed: 2019-06-11 - Published: 2019-09-26 - Granted: 2019-12-10 - Earliest claimed: 2018-03-12 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Matthew David Rowley - Web page: https://patentgrep.com/patent/US10504565B2 ## CPC - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)} - G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips} - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) - G11C 5/141: {Battery and back-up supplies} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A power management integrated circuit (PMIC) receives power from a host and a backup power supply in parallel and uses power from at least one of the host and the backup power supply to operate voltage regulators for a memory system. An enable signal is generated based on whether or not the voltage regulators are powered. The enable signal can be used to keep the backup power supply on while the memory system is in operation. In response to absence of power from the host, the PMIC generates an interrupt signal causing the memory system to shut down safely without data loss. ## Claims ### Claim 1 A power management integrated circuit, comprising: a first power input; a second power input; and at least one voltage regulator operable to generate voltages for a memory system; a sequencer configured to control one or more sequences of power events in the power management integrated circuit; and a circuit configured to combine the first power input and the second power input to power the at least one voltage regulator. ### Claim 2 (depends on 1) The power management integrated circuit of claim 1, wherein the circuit comprises a first diode coupled to the first power input and a second diode coupled to the second power input. ### Claim 3 (depends on 1) The power management integrated circuit of claim 1, wherein when power is available from the first power input, the circuit powers the at least one voltage regulator using at least the power from the first power input. ### Claim 4 (depends on 1) The power management integrated circuit of claim 1, wherein when power is available from the first power input, the circuit is configured to prevent drawing power from the second power input. ### Claim 5 (depends on 4) The power management integrated circuit of claim 4, wherein when power is not available from the first power input, the circuit powers the at least one voltage regulator using power from the second power input. ### Claim 6 (depends on 5) The power management integrated circuit of claim 5, wherein when power is not available from the first power input, the sequencer communicates an interrupt signal to a controller of the memory system. ### Claim 7 (depends on 6) The power management integrated circuit of claim 6, further comprising: an enable signal generator coupled to an output of the circuit configured to combine the first power input and the second power input. ### Claim 8 (depends on 7) The power management integrated circuit of claim 7, wherein: when the at least one voltage regulator is powered by at least one of the first power input and the second power input, the enable signal generator asserts an enable signal; and when the at least one voltage regulator is insufficiently powered by the first power input and the second power input, the enable signal generator de-asserts the enable signal. ### Claim 9 (depends on 7) The power management integrated circuit of claim 7, further comprising: a general-purpose input/output pin connected to provide the enable signal. ### Claim 10 (depends on 8) The power management integrated circuit of claim 8, wherein the enable signal controls operation enabling of a power supply connected to the second power input. ### Claim 11 A system, comprising: a non-volatile memory device; and a power management integrated circuit comprising: at least one voltage regulator configured to generate operating voltages for the non-volatile memory device; a first pin to receive power from a first power source; a second pin to receive power from a second power source; and a circuit configured to combine the first pin and the second pin to power the at least one voltage regulator. ### Claim 12 (depends on 11) The system of claim 11, wherein the circuit comprises: a first diode connected to receive power from the first pin; and a second diode connected to receive power from the second pin; wherein power outputs from the first diode and the second diode are combined and connected as power input to the at least one voltage regulator. ### Claim 13 (depends on 11) The system of claim 11, wherein the circuit is further configured to generate an enable signal based on a status of the power input to the at least one voltage regulator. ### Claim 14 (depends on 13) The system of claim 13, wherein the enable signal controls at least in part operation of the second power source. ### Claim 15 (depends on 13) The system of claim 13, wherein the circuit is further configured to generate an interrupt signal to a controller coupled to the power management integrated circuit in response to absence of power from the first pin. ### Claim 16 A method, comprising: receiving power, from a first power source, in a first pin of a power management integrated circuit; receiving power, from a second power source, in a second pin of the power management integrated circuit; combining, in the power management integrated circuit, power from the first pin and power from the second pin to generate a combined power input; and powering at least one voltage regulator of the power management integrated circuit using the combined power input to generate voltages for a memory device. ### Claim 17 (depends on 16) The method of claim 16, wherein the combining includes combining power from the first pin and power from the second pin using a first diode and a second diode respectively to generate the combined power input to the at least one voltage regulator. ### Claim 18 (depends on 16) The method of claim 16, further comprising: generating an enable signal based on a status of the combined power input to the at least one voltage regulator. ### Claim 19 (depends on 18) The method of claim 18, further comprising: providing the enable signal using a general-purpose input/output pin of the power management integrated circuit to control the second power source. ### Claim 20 (depends on 16) The method of claim 16, further comprising: generating an interrupt signal in response to absence of power in the first pin.