# US 10,504,542 B2 · Increasing storage areal density using predictive data locations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,542 B2 - Document ID: US10504542B2 - Status: Granted - Kind: B2 - Application number: 16/240,934 - Filed: 2019-01-07 - Published: 2019-10-03 - Granted: 2019-12-10 - Earliest claimed: 2018-03-29 - Assignees: Alibaba Group Holding Limited - Applicants: Alibaba Group Holding Limited - Inventors: Shu Li - Web page: https://patentgrep.com/patent/US10504542B2 ## CPC - G11B 5/09: Digital recording - G11B 20/1217: {on discs} - G11B 20/1403: {characterised by the use of two levels} - G11B 2020/1238: {track, i.e. the entire a spirally or concentrically arranged path on which the recording marks are located} - G11B 2020/1292: {Enhancement of the total storage capacity} - G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R) ## Abstract Disclosed are systems, methods, and devices for increasing the storage areal density of a storage device. In one embodiment, a method is disclosed comprising receiving host data, the host data including first data and extra bit data; generating run-length limited (RLL) data by encoding the first data with an RLL encoder; generating a symbol corresponding to at least one bit of the extra bit data; and generating superpositioned data by inserting the symbol within a contiguous section of repeating bits in the RLL-encoded first data. ## Claims ### Claim 1 A method comprising: receiving, by a processor, first data and second data; encoding, by the processor, the first data to generate encoded data; generating, by the processor, a symbol corresponding to the second data; and generating, by the processor, superpositioned data by inserting the symbol within the encoded data. ### Claim 2 (depends on 1) The method of claim 1, the receiving first data and second data comprising receiving the first data and second data as a bitstream. ### Claim 3 (depends on 1) The method of claim 1, the encoding the first data comprising encoding the first data such that the encoded data limits the length of any continuous run of zeros to be within a predefined range. ### Claim 4 (depends on 1) The method of claim 1, the encoding the first data comprising encoding the first data using a run-length limited (RLL) encoder. ### Claim 5 (depends on 1) The method of claim 1, the encoding the first data comprising encoding the first data using a maximum transition run (MTR) encoder. ### Claim 6 An apparatus comprising: one or more processors; and a non-transitory memory storing computer-executable instructions therein that, when executed by the processor, cause the apparatus to perform the operations of: receiving first data and second data; encoding the first data to generate encoded data; generating a symbol corresponding to the second data; and generating superpositioned data by inserting the symbol within the encoded data. ### Claim 7 (depends on 6) The apparatus of claim 6, the receiving first data and second data comprising receiving the first data and second data as a bitstream. ### Claim 8 (depends on 6) The apparatus of claim 6, the encoding the first data comprising encoding the first data such that the encoded data limits the length of any continuous run of zeros to be within a predefined range. ### Claim 9 (depends on 6) The apparatus of claim 6, the encoding the first data comprising encoding the first data using a run-length limited (RLL) encoder. ### Claim 10 (depends on 6) The apparatus of claim 6, the encoding the first data comprising encoding the first data using a maximum transition run (MTR) encoder. ### Claim 11 A method comprising: receiving, by a processor, data, the data including at least one codeword; locating, by the processor, extra bits included in the codeword using a pre-defined preamble pattern; demodulating, by the processor, the extra bits to generate an extra bit portion; and replacing, by the processor, the extra bits in the codeword with the extra bit portion to obtain a second codeword. ### Claim 12 (depends on 11) The method of claim 11, the receiving data comprising reading a hard disk drive sector storing the data. ### Claim 13 (depends on 11) The method of claim 11, further comprising descrambling the data to identify the codeword. ### Claim 14 (depends on 11) The method of claim 11, further comprising decoding the codeword using an error-code correction (ECC) code. ### Claim 15 (depends on 11) The method of claim 11, the locating the extra bits included in the codeword using the pre-defined preamble pattern further comprising locating the extra bits included in the codeword using the pre-defined postamble pattern. ### Claim 16 (depends on 11) The method of claim 11, the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising identifying a repeating pattern of zeros in the codeword, the pattern of zeros representing an invalid sequence in the codeword. ### Claim 17 (depends on 11) The method of claim 11, the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising extracting two bits after the preamble pattern. ### Claim 18 (depends on 11) The method of claim 11, further comprising sequencing the extra bits based on an index of the extra bits in a sequence. ### Claim 19 (depends on 11) The method of claim 11, the demodulating the extra bits to generate the extra bit portion comprising converting a two-bit sequence in the extra bits to a single bit. ### Claim 20 (depends on 11) The method of claim 11, further comprising decoding the second codeword using an encoder selected from the group consisting of a run-length limited (RLL) encoder and a maximum transition run (MTR) encoder. ### Claim 21 (depends on 20) The method of claim 20, further comprising performing, by the processor, a cyclical redundancy check (CRC) on the decoded second codeword. ### Claim 22 An apparatus method comprising: one or more processors; and a non-transitory memory storing computer-executable instructions therein that, when executed by the processor, cause the apparatus to perform the operations of: receiving data, the data including at least one codeword; locating extra bits included in the codeword using a pre-defined preamble pattern; demodulating the extra bits to generate an extra bit portion; and replacing the extra bits in the codeword with the extra bit portion to obtain a second codeword. ### Claim 23 (depends on 22) The apparatus of claim 22, the receiving data comprising reading a hard disk drive sector storing the data. ### Claim 24 (depends on 22) The apparatus of claim 22, further comprising descrambling the data to identify the codeword. ### Claim 25 (depends on 22) The apparatus of claim 22, further comprising decoding the codeword using an error-code correction (ECC) code. ### Claim 26 (depends on 22) The apparatus of claim 22, the locating the extra bits included in the codeword using the pre-defined preamble pattern further comprising locating the extra bits included in the codeword using the pre-defined postamble pattern. ### Claim 27 (depends on 22) The apparatus of claim 22, the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising identifying a repeating pattern of zeros in the codeword, the pattern of zeros representing an invalid sequence in the codeword. ### Claim 28 (depends on 22) The apparatus of claim 22, the locating the extra bits included in the codeword using the pre-defined preamble pattern comprising extracting two bits after the preamble pattern. ### Claim 29 (depends on 22) The apparatus of claim 22, further comprising sequencing the extra bits based on an index of the extra bits in a sequence. ### Claim 30 (depends on 22) The apparatus of claim 22, the demodulating the extra bits to generate the extra bit portion comprising converting a two-bit sequence in the extra bits to a single bit. ### Claim 31 (depends on 22) The apparatus of claim 22, the instructions further causing the apparatus to perform the operation of decoding the second codeword using an encoder selected from the group consisting of a run-length limited (RLL) encoder and a maximum transition run (MTR) encoder. ### Claim 32 (depends on 31) The apparatus of claim 31, the instructions further causing the apparatus to perform the operation of performing a cyclical redundancy check (CRC) on the decoded second codeword.