# US 10,504,479 B2 · Display device

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- Number: US 10,504,479 B2
- Document ID: US10504479B2
- Status: Granted
- Kind: B2
- Application number: 15/708,163
- Filed: 2017-09-19
- Published: 2019-03-21
- Granted: 2019-12-10
- Earliest claimed: 2017-09-19
- Assignees: Innolux Corporation
- Applicants: InnoLux Corporation
- Inventors: Masahiro Yoshiga
- Web page: https://patentgrep.com/patent/US10504479B2

## CPC

- G09G 5/003: {Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092)}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 2300/0857: Static memory circuit, e.g. flip-flop
- G09G 2310/0254: Control of polarity reversal in general, other than for liquid crystal displays
- G09G 2310/06: Details of flat display driving waveforms
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The display panel includes a source line, a common voltage line, a gate line, and a pixel circuit. The pixel circuit includes a first capacitor, a first transistor, a sample circuit, and a memory circuit. The first capacitor is coupled to the common voltage line. The first transistor is coupled to the source line and the first capacitor. The sample circuit includes a second transistor, and the second transistor is coupled to the source line and the first capacitor. The memory circuit is coupled to the first transistor, the sample circuit, and the gate line.

## Claims

### Claim 1

A display device comprising:
a display panel comprising:
a source line;
a common voltage line;
a first control line;
a second control line;
a third control line;
a gate line; and
a pixel circuit comprising:
a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the common voltage line;
a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the source line, and the second terminal of the first transistor is coupled to the second terminal of the first capacitor;
a sample circuit comprising:
a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the source line, and the control terminal of the second transistor is coupled to the second terminal of the first capacitor; and
a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth transistor is coupled to the second terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the second control line; and
a memory circuit comprising:
a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the first control line;
a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor, the second terminal of the third transistor is coupled to the gate line, and the control terminal of the third transistor is coupled to the second terminal of the second capacitor and the first terminal of the fourth transistor; and
a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the third control line, and the second terminal of the third capacitor is coupled to the control terminal of the first transistor.

### Claim 2 (depends on 1)

The display device of claim 1, wherein the memory circuit further comprises:
a fifth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth transistor is coupled to the control terminal of the first transistor, the second terminal of the fifth transistor is coupled to the gate line, and the control terminal of the fifth transistor is coupled to the first terminal of the third capacitor.

### Claim 3 (depends on 2)

The display device of claim 2, wherein:
during an initialization process of the display device:
at a first time point, a voltage of the source line is set to be a reference voltage, a voltage of the gate line is set to be a first high voltage, a voltage of the first control line is set to be the reference voltage, a voltage of the second control line is set to be the first high voltage, and a voltage of the third control line is set to be at a second high voltage;
at a second time, the voltage of the gate line is changed from the first high voltage to the low voltage; and
at a third time, the voltage of the source line is changed from the reference voltage to the low voltage;
the second high voltage is higher than the first high voltage, the first high voltage is higher than the reference voltage, and the reference voltage is higher than the low voltage.

### Claim 4 (depends on 1)

The display device of claim 1, wherein:
when the pixel circuit is in a first polarity mode:
a voltage between the first terminal of the first capacitor and the second the second terminal of the first capacitor is set to be a first data voltage, a second data voltage, a third data voltage, or a fourth data voltage according to pixel data to show;
when the pixel circuit is in a second polarity mode:
the voltage between the first terminal of the first capacitor and the second terminal of the first capacitor is set to be a fifth data voltage, a sixth data voltage, a seventh data voltage, or an eighth data voltage according to pixel data to be show;
the first data voltage and the eighth data voltage substantially have a same magnitude but different polarities;
the second data voltage and the seventh data voltage substantially have a same magnitude but different polarities;
the third data voltage and the sixth data voltage substantially have a same magnitude but different polarities;
the fourth data voltage and the fifth data voltage substantially have a same magnitude but different polarities;
a magnitude of the fourth data voltage is greater than a magnitude of the first data voltage;
the magnitude of the first data voltage is greater than a magnitude of the third data voltage;
the magnitude of the third data voltage is greater than a magnitude of the second data voltage;
the fourth data voltage and the third data voltage have a same polarity;
the third data voltage and the second data voltage have different polarities; and
the second data voltage and the first data voltage have a same polarity.

### Claim 5 (depends on 4)

The display device of claim 4, wherein:
during the first polarity mode of the display device:
at a first time, a voltage of the source line is changed to a low voltage;
at a second time, the voltage of the source line is changed from the low voltage to the first data voltage;
at a third time, a voltage of the first control line is changed from a reference voltage to a first intermediate voltage;
at a fourth time, the voltage of the source line is changed from the first data voltage to the second data voltage;
at a fifth time, the voltage of the first control line is changed from the first intermediate voltage to a second intermediate voltage;
at a sixth time, the voltage of the source line is changed from the second data voltage to the third data voltage;
at a seventh time, the voltage of the first control line is changed from the second intermediate voltage to a third intermediate voltage; and
at an eighth time, a voltage of the second control line is changed from a high voltage to the low voltage;
the low voltage is lower than the first to eighth data voltages;
the high voltage is higher than the first to eighth data voltages;
the first intermediate voltage is substantially equal to the eighth data voltage minus the seventh data voltage plus the second data voltage and minus the first data voltage;
the second intermediate voltage is substantially equal to the eighth data voltage minus the sixth data voltage plus the third data voltage and minus the first data voltage; and
the third intermediate voltage is substantially equal to the eighth data voltage minus the fifth data voltage plus the third data voltage minus the first data voltage, and plus a threshold voltage of the first transistor.

### Claim 6 (depends on 4)

The display device of claim 4, wherein:
during the second polarity mode of the display device:
at a first time, the voltage of the source line is changed from the third data voltage to the eighth data voltage, and the voltage of the first control line is changed from the third intermediate voltage to a fourth intermediate voltage;
at a second time, a voltage of the gate line is changed from the low voltage to a push voltage;
at a third time, the voltage of the first control line is changed from the fourth intermediate voltage to a fifth intermediate voltage;
at a fourth point, the voltage of the gate line is changed from the push voltage to the seventh data voltage;
at a fifth time, the voltage of the source line is changed from the eighth data voltage to the seventh data voltage;
at a sixth time, the voltage of the gate line is changed from the seventh data voltage to the sixth data voltage;
at a seventh time, the voltage of the source line is changed from the seventh data voltage to the sixth data voltage;
at an eighth time, the voltage of the gate line is changed from the sixth data voltage to the fifth data voltage;
at a ninth time, the voltage of the source line is changed from the sixth data voltage to the fifth data voltage;
at a tenth time, the voltage of the gate line is changed from the fifth data voltage to the low voltage; and
at an eleventh time, the voltage of the first control line is changed from the fifth intermediate voltage to the reference voltage, and the voltage of the second control line is changed from the low voltage to the high voltage;
the fourth intermediate voltage is substantially equal to the eighth data voltage minus the first data voltage, and plus three times the threshold voltage;
the fifth intermediate voltage is substantially equal to the eighth data voltage minus the first data voltage, and plus the threshold voltage; and
the push voltage is substantially equal to the eighth data voltage plus the threshold voltage.

### Claim 7 (depends on 1)

The display device of claim 1, wherein:
a voltage between the first terminal of the first capacitor and the second terminal of the first capacitor is set to be a first data voltage, a second data voltage, a third data voltage, or a fourth data voltage according to pixel data to be shown; and
the fourth data voltage is greater than the third data voltage, the third data voltage is greater than the second data voltage, and the second data voltage is greater than the first data voltage.

### Claim 8 (depends on 7)

The display device of claim 7, wherein:
during a refreshing process of the display device:
at a first time, a voltage of the source line is changed to a low voltage;
at a second time, the voltage of the source line is changed from the low voltage to the fourth data voltage;
at a third time, a voltage of the second control line is changed from a high voltage to the low voltage;
at a fourth time, a voltage of the first control line is changed from a reference voltage to a first intermediate voltage;
at a fifth time, a voltage of the gate line is changed from the low voltage to a push voltage;
at a sixth time, the voltage of the first control line is changed from the first intermediate voltage to a second intermediate voltage;
at a seventh time, the voltage of the gate line is changed from the push voltage to the third data voltage;
at an eighth time, the voltage of the source line is changed from the fourth data voltage to the third data voltage;
at a ninth time, the voltage of the gate line is changed from the third data voltage to the second data voltage;
at a tenth time, the voltage of the source line is changed from the third data voltage to the second data voltage;
at an eleventh time, the voltage of the gate line is changed from the second data voltage to the first data voltage;
at a twelfth time, the voltage of the source line is changed from the second data voltage to the first data voltage;
at a thirteenth time, the voltage of the gate line is changed from the first data voltage to the low voltage; and
at a fourteenth time, the voltage of the first control line is changed from the second intermediate voltage to the reference voltage, and the voltage of the second control line is changed from the low voltage to the high voltage;
the low voltage is lower than the first to fourth data voltages;
the high voltage is higher than the first to fourth data voltages;
the first intermediate voltage is substantially equal to three times a threshold voltage of the first transistor;
the second intermediate voltage is substantially equal to the threshold voltage; and
the push voltage is substantially equal to the fourth data voltage plus the threshold voltage.

### Claim 9

A display panel comprising:
a source line;
a common voltage line;
a first control line;
a second control line;
a third control line;
a gate line; and
a pixel circuit comprising:
a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the common voltage line;
a first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the source line, and the second terminal of the first transistor is coupled to the second terminal of the first capacitor;
a sample circuit coupled to the second terminal of the first capacitor and comprising:
a second transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the source line, and the control terminal of the second transistor is coupled to the second terminal of the first capacitor; and
a fourth transistor having a first terminal, a second terminal and a control terminal, wherein the second terminal of the fourth transistor is coupled to the second terminal of the second transistor, and the control terminal of the fourth transistor is coupled to the second control line; and
a memory circuit comprising:
a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the first control line;
a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor, the second terminal of the third transistor is coupled to the gate line, and the control terminal of the third transistor is coupled to the second terminal of the second capacitor and the first terminal of the fourth transistor; and
a third capacitor having a first terminal and a second terminal, wherein the first terminal of the third capacitor is coupled to the third control line, and the second terminal of the third capacitor is coupled to the control terminal of the first transistor.

### Claim 10 (depends on 9)

The display panel of claim 9, wherein the memory circuit further comprises:
a fifth transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the fifth transistor is coupled to the control terminal of the first transistor, the second terminal of the fifth transistor is coupled to the gate line, and the control terminal of the fifth transistor is coupled to the first terminal of the third capacitor.

### Claim 11 (depends on 10)

The display panel of claim 10, wherein:
during an initialization process of the pixel circuit:
at a first time, a voltage of the source line is set to a reference voltage, a voltage of the gate line is set to a first high voltage, a voltage of the first control line is set to be the reference voltage, a voltage of the second control line is set to be the first high voltage, and a voltage of the third control line is set to be a second high voltage;
at a second time, the voltage of the gate line is changed from the first high voltage to the low voltage; and
at a third time, the voltage of the source line is changed from the reference voltage to the low voltage;
the second high voltage is higher than the first high voltage, the first high voltage is higher than the reference voltage, and the reference voltage is higher than the low voltage.

### Claim 12 (depends on 9)

The display panel of claim 9, wherein:
when the pixel circuit is in a first polarity mode:
a voltage between the first terminal and the second terminal of the first capacitor is set to be a first data voltage, a second data voltage, a third data voltage, or a fourth data voltage according to pixel data to be shown;
when the pixel circuit is in a second polarity mode:
the voltage between the first terminal and the second terminal of the first capacitor is set to be a fifth data voltage, a sixth data voltage, a seventh data voltage, or an eighth data voltage according to pixel data to be shown;
the first data voltage and the eighth data voltage substantially have a same magnitude but different polarities;
the second data voltage and the seventh data voltage substantially have a same magnitude but different polarities;
the third data voltage and the sixth data voltage substantially have a same magnitude but different polarities;
the fourth data voltage and the fifth data voltage substantially have a same magnitude but different polarities;
a magnitude of the fourth data voltage is greater than a magnitude of the first data voltage;
the magnitude of the first data voltage is greater than a magnitude of the third data voltage;
the magnitude of the third data voltage is greater than a magnitude of the second data voltage;
the fourth data voltage and the third data voltage have a same polarity;
the third data voltage and the second data voltage have different polarities; and
the second data voltage and the first data voltage have a same polarity.

### Claim 13 (depends on 12)

The display panel of claim 12, wherein:
during the first polarity mode of the display panel:
at a first time, a voltage of the source line is changed to a low voltage;
at a second time, the voltage of the source line is changed from the low voltage to the first data voltage;
at a third time, a voltage of the first control line is changed from a reference voltage to a first intermediate voltage;
at a fourth time, the voltage of the source line is changed from the first data voltage to the second data voltage;
at a fifth time, the voltage of the first control line is changed from the first intermediate voltage to a second intermediate voltage the;
at a sixth time, the voltage of the source line is changed from the second data voltage to the third data voltage;
at a seventh time, the voltage of the first control line is changed from the second intermediate voltage to a third intermediate voltage; and
at an eighth time, a voltage of the second control line is changed from a high voltage to the low voltage;
the low voltage is lower than the first to eighth data voltages;
the high voltage is higher than the first to eighth data voltages;
the first intermediate voltage is substantially equal to the eighth data voltage minus the seventh data voltage plus the second data voltage and minus the first data voltage;
the second intermediate voltage is substantially equal to the eighth data voltage minus the sixth data voltage plus the third data voltage and minus the first data voltage; and
the third intermediate voltage is substantially equal to the eighth data voltage minus the fifth data voltage plus the third data voltage minus the first data voltage, and plus a threshold voltage of the first transistor.

### Claim 14 (depends on 12)

The display panel of claim 12, wherein:
during the second polarity mode of the display panel:
at a first time, the voltage of the source line is changed from the third data voltage to the eighth data voltage, and the voltage of the first control line is changed from the third intermediate voltage to a fourth intermediate voltage;
at a second time, a voltage of the gate line is changed from the low voltage to a push voltage;
at a third time, the voltage of the first control line is changed from the fourth intermediate voltage to a fifth intermediate voltage;
at a fourth point, the voltage of the gate line is changed from the push voltage to the seventh data voltage;
at a fifth time, the voltage of the source line is changed from the eighth data voltage to the seventh data voltage;
at a sixth time, the voltage of the gate line is changed from the seventh data voltage to the sixth data voltage;
at a seventh time, the voltage of the source line is changed from the seventh data voltage to the sixth data voltage;
at an eighth time, the voltage of the gate line is changed from the sixth data voltage to the fifth data voltage;
at a ninth time, the voltage of the source line is changed from the sixth data voltage to the fifth data voltage;
at a tenth time, the voltage of the gate line is changed from the fifth data voltage to the low voltage; and
at an eleventh time, the voltage of the first control line is changed from the fifth intermediate voltage to the reference voltage, and the voltage of the second control line is changed from the low voltage to the high voltage;
the fourth intermediate voltage is substantially equal to the eighth data voltage minus the first data voltage, and plus three times the threshold voltage;
the fifth intermediate voltage is substantially equal to the eighth data voltage minus the first data voltage, and plus the threshold voltage; and
the push voltage is substantially equal to the eighth data voltage plus the threshold voltage.

### Claim 15 (depends on 9)

The display panel of claim 9, wherein:
a voltage between the first terminal and the second terminal of the first capacitor is set to be a first data voltage, a second data voltage, a third data voltage, or a fourth data voltage according to pixel data to be shown; and
the fourth data voltage is greater than the third data voltage, the third data voltage is greater than the second data voltage, and the second data voltage is greater than the first data voltage.

### Claim 16 (depends on 15)

The display panel of claim 15, wherein:
during a refreshing process of the display panel:
at a first time, a voltage of the source line is changed to a low voltage;
at a second time, the voltage of the source line is changed from the low voltage to the fourth data voltage;
at a third time, a voltage of the second control line is changed from a high voltage to the low voltage;
at a fourth time, a voltage of the first control line is changed from a reference voltage to a first intermediate voltage;
at a fifth time, a voltage of the gate line is changed from the low voltage to a push voltage;
at a sixth time, the voltage of the first control line is changed from the first intermediate voltage to a second intermediate voltage;
at a seventh time, the voltage of the gate line is changed from the push voltage to the third data voltage;
at an eighth time, the voltage of the source line is changed from the fourth data voltage to the third data voltage;
at a ninth time, the voltage of the gate line is changed from the third data voltage to the second data voltage;
at a tenth time, the voltage of the source line is changed from the third data voltage to the second data voltage;
at an eleventh time, the voltage of the gate line is changed from the second data voltage to the first data voltage;
at a twelfth time, the voltage of the source line is changed from the second data voltage to the first data voltage;
at a thirteenth time, the voltage of the gate line is changed from the first data voltage to the low voltage;
at a fourteenth time, the voltage of the first control line is changed from the second intermediate voltage to the reference voltage, and the voltage of the second control line is changed from the low voltage to the high voltage;
the low voltage is lower than the first to fourth data voltages;
the high voltage is higher than the first to fourth data voltages;
the first intermediate voltage is substantially equal to three times a threshold voltage of the first transistor;
the second intermediate voltage is substantially equal to the threshold voltage; and
the push voltage is substantially equal to the fourth data voltage plus the threshold voltage.