# US 10,504,469 B2 · Shift-buffer circuit, gate driving circuit, display panel and driving method

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- Number: US 10,504,469 B2
- Document ID: US10504469B2
- Status: Granted
- Kind: B2
- Application number: 15/768,948
- Filed: 2017-10-17
- Published: 2019-02-21
- Granted: 2019-12-10
- Earliest claimed: 2017-04-05
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Jiha Kim; Seung Woo Han; Guangliang Shang; Xing Yao; Haoliang Zheng; Mingfu Han; Zhichong Wang; Lijun Yuan; Yun Sik Im; Jing Lv; Yinglong Huang; Xue Dong
- Web page: https://patentgrep.com/patent/US10504469B2

## CPC

- G09G 3/3677: {suitable for active matrices only}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3266: Details of drivers for scan electrodes
- G11C 19/184: {with field-effect transistors, e.g. MOS-FET}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0408: Integration of the drivers onto the display substrate
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

## Claims

### Claim 1

A shift-buffer circuit, comprising: a shift register and a plurality of buffers connected with the shift register, wherein:
the shift register comprises a shift output terminal;
the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal;
each of the buffers comprises a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; and
each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal,
wherein each of the buffers comprises:
a buffer input circuit, connected with the buffer input terminal and a buffer pull-up node respectively;
a first buffer reset circuit, connected with the buffer pull-up node, a first buffer pull-down node and a second power supply terminal respectively;
a buffer output circuit, connected with the buffer pull-up node, a buffer clock signal terminal and the buffer output terminal respectively;
a first buffer output pull-down circuit, connected with the buffer output terminal, the first buffer pull-down node and the second power supply terminal respectively; and
a buffer storage capacitor, connected with the buffer pull-up node and the buffer output terminal respectively.

### Claim 2 (depends on 1)

The shift-buffer circuit according to claim 1, wherein the shift register comprises:
a shift input circuit, connected with a shift input terminal and a shift pull-up node respectively;
a first shift reset circuit, connected with the shift pull-up node, a first shift pull-down node, and a first power supply terminal respectively;
a shift output circuit, connected with the shift pull-up node, a shift clock signal terminal and the shift output terminal respectively;
a first shift output pull-down circuit, connected with the shift output terminal, the first shift pull-down node and the first power supply terminal respectively;
a first pull-down node control circuit, connected with the first shift pull-down node, a first power signal terminal and the first power supply terminal respectively; and
a shift storage capacitor, connected with the shift pull-up node and the shift output terminal respectively.

### Claim 3 (depends on 2)

The shift-buffer circuit according to claim 2, wherein the second power supply terminal is connected with the first power supply terminal, and the first buffer pull-down node is connected with the first shift pull-down node.

### Claim 4 (depends on 3)

The shift-buffer circuit according to claim 3, wherein:
the shift input circuit comprises a first shift transistor, a first electrode of the first shift transistor being connected with the shift input terminal, a gate electrode of the first shift transistor being connected with the shift input terminal, and a second electrode of the first shift transistor being connected with the shift pull-up node;
the first shift reset circuit comprises a second shift transistor, a first electrode of the second shift transistor being connected with the shift pull-up node, a gate electrode of the second shift transistor being connected with the first shift pull-down node, and a second electrode of the second shift transistor being connected with the first power supply terminal;
the shift output circuit comprises a third shift transistor, a first electrode of the third shift transistor being connected with the shift clock signal terminal, a gate electrode of the third shift transistor being connected with the shift pull-up node, and a second electrode of the third shift transistor being connected with the shift output terminal;
the first shift output pull-down circuit comprises a fourth shift transistor, a first electrode of the fourth shift transistor being connected with the shift output terminal, a gate electrode of the fourth shift transistor being connected with the first shift pull-down node, and a second electrode of the fourth shift transistor being connected with the first power supply terminal;
the first pull-down node control circuit comprises a fifth shift transistor and a sixth shift transistor, a first electrode of the fifth shift transistor being connected with the first power signal terminal, a gate electrode of the fifth transistor being connected with the first power signal terminal, a second electrode of the fifth shift transistor being connected with the first shift pull-down node, a first electrode of the sixth shift transistor being connected with the first shift pull-down node, a gate electrode of the sixth shift transistor being connected with the shift pull-up node, and a second electrode of the sixth shift transistor being connected with the first power supply terminal; and
a first terminal of the shift storage capacitor is connected with the shift pull-up node, and a second terminal of the shift storage capacitor is connected with the shift output terminal.

### Claim 5 (depends on 3)

The shift-buffer circuit according to claim 3, wherein:
the buffer input circuit comprises a first buffer transistor, a first electrode of the first buffer transistor being connected with the buffer input terminal, a gate electrode of the first buffer transistor being connected with an enabled signal terminal, and a second electrode of the first buffer transistor being connected with the buffer pull-up node;
the first buffer reset circuit comprises a second buffer transistor, a first electrode of the second buffer transistor being connected with the buffer pull-up node, a gate electrode of the second buffer transistor being connected with the first buffer pull-down node, and a second electrode of the second buffer transistor being connected with the second power supply terminal;
the buffer output circuit comprises a third buffer transistor, a first electrode of the third buffer transistor being connected with the buffer clock signal terminal, a gate electrode of the third buffer transistor being connected with the buffer pull-up node, and a second electrode of the third buffer transistor being connected with the buffer output terminal;
the first buffer output pull-down circuit comprises a fourth buffer transistor, a first electrode of the fourth buffer transistor being connected with the buffer output terminal, a gate electrode of the fourth buffer transistor being connected with the first buffer pull-down node, and a second electrode of the fourth buffer transistor being connected with the second power supply terminal; and
a first terminal of the buffer storage capacitor is connected with the buffer pull-up node, and a second terminal of the buffer storage capacitor is connected with the buffer output terminal.

### Claim 6 (depends on 3)

The shift-buffer circuit according to claim 3, wherein:
the shift register further comprises:
a second shift reset circuit, connected with the shift pull-up node, a second shift pull-down node and a first power supply terminal respectively;
a second shift output pull-down circuit, connected with the shift output terminal, the second shift pull-down node and the first power supply terminal respectively; and
a second pull-down node control circuit, connected with the second shift pull-down node, a second power signal terminal and the first power supply terminal respectively; and
each of the buffers further comprises:
a second buffer reset circuit, connected with the buffer pull-up node, a second buffer pull-down node and the second power supply terminal respectively; and
a second buffer output pull-down circuit, connected with the buffer output terminal, the second buffer pull-down node and the second power supply terminal respectively,
wherein a first power signal provided by the first power signal terminal and a second power signal provided by the second power signal terminal are mutually reverse signals.

### Claim 7 (depends on 2)

The shift-buffer circuit according to claim 2, wherein:
the shift input circuit comprises a first shift transistor, a first electrode of the first shift transistor being connected with the shift input terminal, a gate electrode of the first shift transistor being connected with the shift input terminal, and a second electrode of the first shift transistor being connected with the shift pull-up node;
the first shift reset circuit comprises a second shift transistor, a first electrode of the second shift transistor being connected with the shift pull-up node, a gate electrode of the second shift transistor being connected with the first shift pull-down node, and a second electrode of the second shift transistor being connected with the first power supply terminal;
the shift output circuit comprises a third shift transistor, a first electrode of the third shift transistor being connected with the shift clock signal terminal, a gate electrode of the third shift transistor being connected with the shift pull-up node, and a second electrode of the third shift transistor being connected with the shift output terminal;
the first shift output pull-down circuit comprises a fourth shift transistor, a first electrode of the fourth shift transistor being connected with the shift output terminal, a gate electrode of the fourth shift transistor being connected with the first shift pull-down node, and a second electrode of the fourth shift transistor being connected with the first power supply terminal;
the first pull-down node control circuit comprises a fifth shift transistor and a sixth shift transistor, a first electrode of the fifth shift transistor being connected with the first power signal terminal, a gate electrode of the fifth transistor being connected with the first power signal terminal, a second electrode of the fifth shift transistor being connected with the first shift pull-down node, a first electrode of the sixth shift transistor being connected with the first shift pull-down node, a gate electrode of the sixth shift transistor being connected with the shift pull-up node, and a second electrode of the sixth shift transistor being connected with the first power supply terminal; and
a first terminal of the shift storage capacitor is connected with the shift pull-up node, and a second terminal of the shift storage capacitor is connected with the shift output terminal.

### Claim 8 (depends on 2)

The shift-buffer circuit according to claim 2, wherein:
the shift register further comprises:
a second shift reset circuit, connected with the shift pull-up node, a second shift pull-down node and a first power supply terminal respectively;
a second shift output pull-down circuit, connected with the shift output terminal, the second shift pull-down node and the first power supply terminal respectively; and
a second pull-down node control circuit, connected with the second shift pull-down node, a second power signal terminal and the first power supply terminal respectively; and
each of the buffers further comprises:
a second buffer reset circuit, connected with the buffer pull-up node, a second buffer pull-down node and the second power supply terminal respectively; and
a second buffer output pull-down circuit, connected with the buffer output terminal, the second buffer pull-down node and the second power supply terminal respectively,
wherein a first power signal provided by the first power signal terminal and a second power signal provided by the second power signal terminal are mutually reverse signals.

### Claim 9 (depends on 8)

The shift-buffer circuit according to claim 8, wherein:
the second shift reset circuit comprises a seventh shift transistor, a first electrode of the seventh shift transistor being connected with the shift pull-up node, a gate electrode of the seventh shift transistor being connected with the second shift pull-down node, and a second electrode of the seventh shift transistor being connected with the first power supply terminal;
the second shift output pull-down circuit comprises an eighth shift transistor, a first electrode of the eighth shift transistor being connected with the shift output terminal, a gate electrode of the eighth shift transistor being connected with the second shift pull-down node, and a second electrode of the eighth shift transistor being connected with the first power supply terminal;
the second pull-down node control circuit comprises a ninth shift transistor and a tenth shift transistor, a first electrode of the ninth shift transistor being connected with the second power signal terminal, a gate electrode of the ninth shift transistor being connected with the second power signal terminal, a second electrode of the ninth shift transistor being connected with the second shift pull-down node, a first electrode of the tenth shift transistor being connected with the second shift pull-down node, a gate electrode of the tenth shift transistor being connected with the shift pull-up node, and a second electrode of the tenth shift transistor being connected with the first power supply terminal;
the second buffer reset circuit comprises a fifth buffer transistor, a first electrode of the fifth buffer transistor being connected with the buffer pull-up node, a gate electrode of the fifth buffer transistor being connected with the second buffer pull-down node, and a second electrode of the fifth buffer transistor being connected with the second power supply terminal; and
the second buffer output pull-down circuit comprises a sixth buffer transistor, a first electrode of the sixth buffer transistor being connected with the buffer output terminal, a gate electrode of the sixth buffer transistor being connected with the second buffer pull-down node, and a second electrode of the sixth buffer transistor being connected with the second power supply terminal.

### Claim 10 (depends on 8)

The shift-buffer circuit according to claim 8, wherein the second buffer pull-down node is connected with the second shift pull-down node.

### Claim 11 (depends on 1)

The shift-buffer circuit according to claim 1, wherein:
the buffer input circuit comprises a first buffer transistor, a first electrode of the first buffer transistor being connected with the buffer input terminal, a gate electrode of the first buffer transistor being connected with an enabled signal terminal, and a second electrode of the first buffer transistor being connected with the buffer pull-up node;
the first buffer reset circuit comprises a second buffer transistor, a first electrode of the second buffer transistor being connected with the buffer pull-up node, a gate electrode of the second buffer transistor being connected with the first buffer pull-down node, and a second electrode of the second buffer transistor being connected with the second power supply terminal;
the buffer output circuit comprises a third buffer transistor, a first electrode of the third buffer transistor being connected with the buffer clock signal terminal, a gate electrode of the third buffer transistor being connected with the buffer pull-up node, and a second electrode of the third buffer transistor being connected with the buffer output terminal;
the first buffer output pull-down circuit comprises a fourth buffer transistor, a first electrode of the fourth buffer transistor being connected with the buffer output terminal, a gate electrode of the fourth buffer transistor being connected with the first buffer pull-down node, and a second electrode of the fourth buffer transistor being connected with the second power supply terminal; and
a first terminal of the buffer storage capacitor is connected with the buffer pull-up node, and a second terminal of the buffer storage capacitor is connected with the buffer output terminal.

### Claim 12 (depends on 1)

The shift-buffer circuit according to claim 1, wherein each of the shift registers is connected with four of the buffers.

### Claim 13 (depends on 1)

A gate driving circuit, comprising shift-buffer circuits in a plurality of stages, wherein a shift-buffer circuit of each stage comprises the shift-buffer circuit according to claim 1.

### Claim 14 (depends on 13)

The gate driving circuit according to claim 13, wherein:
a shift output terminal of a shift register in a shift-buffer circuit of a (2n−1)-th stage is connected with a shift input terminal of a shift register in a shift-buffer circuit of a (2n+1)-th stage; and
a shift output terminal of a shift register in a shift-buffer circuit of a 2n-th stage is connected with a shift input terminal of a shift register in a shift-buffer circuit of a (2n+2)-th stage,
where n is an integer greater than zero.

### Claim 15 (depends on 14)

The gate driving circuit according to claim 14, wherein:
an enabled signal terminal of a buffer in the shift-buffer circuit of the (2n−1)-th stage is configured to receive a first enabled signal; and
an enabled signal terminal of a buffer in the shift-buffer circuit of the 2n-th stage is configured to receive a second enabled signal.

### Claim 16 (depends on 13)

A display panel, comprising the gate driving circuit according to claim 13.

### Claim 17 (depends on 16)

A display device, comprising the display panel according to claim 16.

### Claim 18 (depends on 1)

A method of driving the shift-buffer circuit according to claim 1, comprising:
applying a shift clock signal to a shift register, to make the shift register output a shift output signal in response to the shift clock signal; and
applying buffer clock signals to a plurality of buffers in a period of the shift output signal, to make the plurality of buffers output buffer output signals sequentially.