# US 10,504,467 B2 · Display device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,467 B2 - Document ID: US10504467B2 - Status: Granted - Kind: B2 - Application number: 15/485,659 - Filed: 2017-04-12 - Published: 2017-10-26 - Granted: 2019-12-10 - Earliest claimed: 2016-04-20 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Yoon-Jang Kim; Kwi Hyun Kim; Sung Ryul Kim; Yun Seok Lee; Wan-Soon Im - Web page: https://patentgrep.com/patent/US10504467B2 ## CPC - G09G 3/3677: {suitable for active matrices only} - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate} - H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon} - H10D 30/6723: {having light shields} - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10K 59/1315: {comprising structures specially adapted for lowering the resistance} - G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F 2201/123: pixel - G02F 2202/104: poly-Si - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A display device including a substrate, a gate driver disposed on the substrate and including a plurality of stages, a clock signal line disposed on the substrate, and transmitting a clock signal to at least one of the stages, a transistor disposed on the substrate, and a light blocking layer disposed between the substrate and the transistor and overlapping the transistor. The clock signal line includes a first conductive line and a second conductive line overlapping the first conductive line, and the first conductive line is disposed in the same layer as the light blocking layer. ## Claims ### Claim 1 A display device comprising: a substrate; a gate driver disposed on the substrate and including a plurality of stages; a clock signal line disposed on the substrate and transmitting a clock signal to at least one of the stages; a transistor disposed on the substrate; and a light blocking layer disposed between the substrate and the transistor and overlapping the transistor wherein the clock signal line includes a first conductive line and a second conductive line overlapping the first conductive line, and the first conductive line is disposed in the same layer as the light blocking layer. ### Claim 2 (depends on 1) The display device of claim 1, wherein the clock signal line is connected to the at least one stage by a connector, and the first conductive line is electrically connected to the second conductive line by the connector. ### Claim 3 (depends on 2) The display device of claim 2, wherein the second conductive line includes a cutout overlapping the first conductive line, and the connector is connected to the first conductive line through the cutout. ### Claim 4 (depends on 3) The display device of claim 3, further comprising: a first insulating layer disposed between the first conductive line and the second conductive line; and a second insulating layer disposed on the first and second conductive lines, wherein the connector is connected to the second conductive line through a first contact hole formed in the second insulating layer and is connected to the first conductive line through a second contact hole formed in the first and second insulating layers. ### Claim 5 (depends on 4) The display device of claim 4, further comprising an insulator disposed between the first insulating layer and the second conductive line and having a planar shape substantially the same as that of the second conductive line. ### Claim 6 (depends on 1) The display device of claim 1, wherein the first conductive line includes a first opening, and the second conductive line includes a second opening overlapping the first opening. ### Claim 7 (depends on 2) The display device of claim 2, wherein the transistor includes a gate electrode, a source electrode, a drain electrode, and a semiconductor, and the second conductive line is disposed in the same layer as the gate electrode of the transistor. ### Claim 8 (depends on 7) The display device of claim 7, wherein the connector is disposed in the same layer as the source electrode and the drain electrode of the transistor. ### Claim 9 (depends on 7) The display device of claim 7, wherein the semiconductor is disposed between the light blocking layer and the gate electrode. ### Claim 10 (depends on 7) The display device of claim 7, wherein the source electrode is electrically connected to the light blocking layer. ### Claim 11 (depends on 2) The display device of claim 2, further comprising a pixel electrode connected to the transistor, wherein the connector is disposed in the same layer as the pixel electrode.