# US 10,504,448 B2 · Display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,448 B2 - Document ID: US10504448B2 - Status: Granted - Kind: B2 - Application number: 15/789,231 - Filed: 2017-10-20 - Published: 2018-05-03 - Granted: 2019-12-10 - Earliest claimed: 2016-11-03 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Sunghwan Kim; Junhyun Park; Kyoungju Shin; Chongchul Chai - Web page: https://patentgrep.com/patent/US10504448B2 ## CPC - G09G 3/3275: Details of drivers for data electrodes - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3266: Details of drivers for scan electrodes - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0871: with level shifting - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/06: Details of flat display driving waveforms - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display apparatus includes a first pixel connected to a first scan line, a second scan line, and a first data line, a second pixel connected to the first scan line and a second data line, and a selection circuit configured to electrically connect a first channel to one of the first data line and the second data line in response to selection signals. A pulse width of a first scan signal configured to be provided to the first scan line and a pulse width of a second scan signal configured to be provided to the second scan line are longer than one horizontal period. ## Claims ### Claim 1 A display apparatus comprising: a first pixel connected to a first scan line, a second scan line, and a first data line; a second pixel connected to the first scan line and a second data line; and a selection circuit configured to electrically connect a first channel to one of the first data line and the second data line in response to selection signals, wherein a pulse width of a first scan signal configured to be provided to the first scan line and a pulse width of a second scan signal configured to be provided to the second scan line are longer than one horizontal period, wherein the first pixel comprises: a first transistor comprising a first electrode, a second electrode connected to a first node, and a gate electrode connected to the first scan line; a first light emitting unit connected to the first node, and configured to receive a first voltage and a second voltage and to emit a light; and a first switching transistor comprising a first electrode connected to the first data line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the second scan line, wherein one of the first transistor and the first switching transistor is a PMOS transistor, and the other is an NMOS transistor. ### Claim 2 (depends on 1) The display apparatus of claim 1, wherein the first scan signal and the second scan signal are configured to be sequentially activated, and an active period of the first scan signal partially overlaps with an active period of the second scan signal. ### Claim 3 (depends on 1) The display apparatus of claim 1, wherein the first light emitting unit comprises: a second transistor comprising a first electrode configured to receive the first voltage, a second electrode connected to a second node, and a gate electrode connected to the first node; a capacitor connected to and between the first node and the second node; and a first light emitting device comprising one end connected to the second node and the other end configured to receive the second voltage. ### Claim 4 (depends on 1) The display apparatus of claim 1, wherein the first transistor is a PMOS transistor, and the first switching transistor is an NMOS transistor. ### Claim 5 (depends on 1) The display apparatus of claim 1, wherein, when the second scan signal transmitted through the second scan line is inactive and the first scan signal transmitted through the first scan line is active, a first data signal transmitted through the first data line is provided to the first node. ### Claim 6 (depends on 5) The display apparatus of claim 5, wherein a period in which the second scan signal transmitted through the second scan line is inactive and the first scan signal transmitted through the first scan line is active is equal to the one horizontal period. ### Claim 7 (depends on 5) The display apparatus of claim 5, wherein, when the first scan signal transmitted through the first scan line is active, a second data signal transmitted through the second data line is provided to the second pixel. ### Claim 8 (depends on 1) The display apparatus of claim 1, wherein the first transistor is an NMOS transistor, and the first switching transistor is a PMOS transistor. ### Claim 9 A display apparatus comprising: a first pixel connected to a first scan line, a second scan line, and a first data line; a second pixel connected to the first scan line and a second data line; a third pixel connected to the second scan line, a third scan line, and the first data line; and a fourth pixel connected to the second scan line and the second data line, a selection circuit configured to electrically connect a first channel to one of the first data line and the second data line in response to selection signals, wherein the first pixel comprises: a first transistor comprising a first electrode, a second electrode connected to a first node, and a gate electrode connected to the first scan line; a first light emitting unit connected to the first node, and configured to receive a first voltage and a second voltage and to emit a light; and a first switching transistor comprising a first electrode connected to the first data line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the second scan line, wherein the third pixel comprises: a third transistor comprising a first electrode, a second electrode connected to a third node, and a gate electrode connected to the second scan line; a third light emitting unit connected to the third node, and configured to receive a first voltage and a second voltage and to emit a light; and a third switching transistor comprising a first electrode connected to the first data line, a second electrode connected to the first electrode of the third transistor, and a gate electrode connected to the third scan line, wherein each of the first transistor and the first switching transistor is a first type transistor, and each of the third transistor and the third switching transistor is a second type transistor different from the first type transistor. ### Claim 10 (depends on 9) The display apparatus of claim 9, wherein the third light emitting unit comprises: a fourth transistor comprising a first electrode configured to receive the first voltage, a second electrode connected to a fourth node, and a gate electrode connected to the third node; a capacitor connected to and between the third node and the fourth node; and a second light emitting device comprising one end connected to the fourth node and the other end configured to receive the second voltage. ### Claim 11 (depends on 10) The display apparatus of claim 10, wherein the first transistor is a PMOS transistor, the third transistor is an NMOS transistor, the first switching transistor comprises a PMOS transistor, and the third switching transistor comprises an NMOS transistor. ### Claim 12 (depends on 1) The display apparatus of claim 1, wherein the second pixel is further connected to a third scan line, and the second pixel comprises: a second pixel circuit connected to the first scan line; and a second switching circuit which is configured to provide a second data signal, which is provided from the second data line, to the second pixel circuit in response to a third scan signal provided through the third scan line. ### Claim 13 (depends on 12) The display apparatus of claim 12, wherein the first scan signal and the third scan signal comprise an active period having a first level, and the second scan signal comprises an active period having a second level. ### Claim 14 (depends on 12) The display apparatus of claim 12, wherein the second scan signal and the third scan signal are sequentially activated, and an active period of the second scan signal partially overlaps with an active period of the third scan signal. ### Claim 15 (depends on 1) The display apparatus of claim 1, further comprising: a gate driving circuit which is configured to drive the first scan line using the first scan signal and the second scan line using the second scan signal; a data driving circuit which is configured to sequentially output a first data signal and a second data signal to the first channel; and a driving controller configured to control the data driving circuit and the gate driving circuit. ### Claim 16 (depends on 1) The display apparatus of claim 1, wherein the selection signals comprise a first selection signal and a second selection signal, and the selection circuit comprises: a first switching device configured to electrically connect the first channel to the first data line in response to the first selection signal; and a second switching device configured to electrically connect the first channel to the second data line in response to the second selection signal. ### Claim 17 A display apparatus comprising: a selection circuit configured to electrically connect a first channel to one of a first data line and a second data line in response to selection signals; a first pixel circuit connected to a first scan line; a first switching circuit connected to and between the first data line and the first pixel circuit configured to provide a first data signal, which is provided from the first data line, to the first pixel circuit in response to a second scan signal from a second scan line; and a second pixel connected to the first scan line and the second data line, wherein a pulse width of a first scan signal configured to be provided to the first scan line and a pulse width of the second scan signal configured to be provided to the second scan line are longer than one horizontal period, wherein the first scan signal and the second scan signal are configured to be sequentially activated, and an active period of the first scan signal partially overlaps with an active period of the second scan signal, wherein a period, in which the second scan signal configured to be transmitted through the second scan line is inactive and the first scan signal configured to be transmitted through t he first scan line is active, is equal to the one horizontal period.