# US 10,504,441 B2 · Pixel internal compensation circuit and driving method

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- Number: US 10,504,441 B2
- Document ID: US10504441B2
- Status: Granted
- Kind: B2
- Application number: 15/744,829
- Filed: 2017-11-16
- Published: 2019-02-28
- Granted: 2019-12-10
- Earliest claimed: 2017-08-24
- Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
- Inventors: Jian He; Shensian Syu
- Web page: https://patentgrep.com/patent/US10504441B2

## CPC

- G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2320/0233: Improving the luminance or brightness uniformity across the screen
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The invention discloses a pixel internal compensation circuit and riving method. The pixel internal compensation circuit comprises: first TFT (T1), with gate connected to third control signal (SCAN3), source and drain connected to data voltage (Vdata) and first node (A); second TFT (T2), with gate connected to first node (A), source and drain connected to second node (B) and high voltage power source (OVDD); third TFT (T3), with gate connected to first control signal (SCAN1), source and drain connected to first node (A) and reference voltage (Vref); fourth TFT (T4), with gate connected to second control signal (SCAN2), source and drain connected to second node (B) and initial voltage (Vini); capacitor C1, with two ends connected to first node (A) and second node (B); OLED, with anode connected to second node (B), and cathode connected to low voltage power source (OVSS). The invention provides a corresponding driving method. The invention uses parallel driving mode to effectively increase sensing time of threshold voltage compensation to improve compensation effect.

## Claims

### Claim 1

A pixel internal compensation circuit, which comprises:
a first thin film transistor (TFT), having a gate connected to a third control signal, a source and a drain connected respectively to a data voltage and a first node;
a second TFT, having a gate connected to the first node, a source and a drain connected respectively to a second node and a high voltage power source;
a third TFT, having a gate connected to a first control signal, a source and a drain connected respectively to the first node and a reference voltage;
a fourth TFT, having a gate connected to a second control signal, a source and a drain connected respectively to the second node and an initial voltage;
a capacitor, having two ends connected respectively to the first node and the second node;
an OLED, having an anode connected to the second node, and a cathode connected to a low voltage power source
wherein the initial voltage is less than activation voltage of the OLED, and a difference between reference voltage and initial voltage (reference voltage−initial voltage) is greater than threshold voltage of the second TFT;
wherein the first control signal, the second control signal, and the third control signal have timing sequence configured for a reset phase, a sensing phase, a data write-in phase, and a light-emitting phase; and
wherein the first control signal, the second control signal, and the third control signal of pixels of a current row and the first control signal, the second control signal, and the third control signal of pixels of an adjacent row are configured so that the data write-in phase of the pixels of the current row and the data write-in phase of the pixels of the adjacent row do not overlap, and the reset phase and the sensing phase of the pixels of the current row respectively overlap the reset phase and the sensing phase of the pixels of the adjacent row.

### Claim 2 (depends on 1)

The pixel internal compensation circuit as claimed in claim 1, wherein in the reset phase, the first control signal is at high voltage, the second control signal is at high voltage, and the third control signal is at low voltage.

### Claim 3 (depends on 1)

The pixel internal compensation circuit as claimed in claim 1, wherein in the sensing phase, the first control signal is at high voltage, the second control signal is at low voltage, and the third control signal is at low voltage.

### Claim 4 (depends on 1)

The pixel internal compensation circuit as claimed in claim 1, wherein in the data write-in phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at high voltage.

### Claim 5 (depends on 1)

The pixel internal compensation circuit as claimed in claim 1, wherein in the light-emitting phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at low voltage.

### Claim 6 (depends on 1)

A driving method of the pixel internal compensation circuit as claimed in claim 1, comprising: the first control signal, the second control signal, and the third control signal having timing sequence configured for a reset phase, a sensing phase, a data write-in phase, and a light-emitting phase, wherein the first control signal, the second control signal, and the third control signal of pixels of a current row and the first control signal, the second control signal, and the third control signal of pixels of an adjacent row are configured so that the data write-in phase of the pixels of the current row and the data write-in phase of the pixels of the adjacent row do not overlap, and the reset phase and the sensing phase of the pixels of the current row respectively overlap the reset phase and the sensing phase of the pixels of the adjacent row.

### Claim 7 (depends on 6)

The driving method of pixel internal compensation circuit as claimed in claim 6, wherein in the reset phase, the first control signal is at high voltage, the second control signal is at high voltage, and the third control signal is at low voltage; in the sensing phase, the first control signal is at high voltage, the second control signal is at low voltage, and the third control signal is at low voltage; in the data write-in phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at high voltage; in the light-emitting phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at low voltage.

### Claim 8

A pixel internal compensation circuit, which comprises:
a first thin film transistor (TFT), having a gate connected to a third control signal, a source and a drain connected respectively to a data voltage and a first node;
a second TFT, having a gate connected to the first node, a source and a drain connected respectively to a second node and a high voltage power source;
a third TFT, having a gate connected to a first control signal, a source and a drain connected respectively to the first node and a reference voltage;
a fourth TFT, having a gate connected to a second control signal, a source and a drain connected respectively to the second node and an initial voltage;
a capacitor, having two ends connected respectively to the first node and the second node;
an OLED, having an anode connected to the second node, and a cathode connected to a low voltage power source;
wherein the initial voltage is less than activation voltage of the OLED, and the difference between reference voltage and initial voltage (reference voltage−initial voltage) is greater than threshold voltage of the second TFT;
wherein the first control signal, the second control signal, and the third control signal have timing sequence configured for a reset phase, a sensing phase, a data write-in phase, and a light-emitting phase;
wherein in the reset phase, the first control signal is at high voltage, the second control signal is at high voltage, and the third control signal is at low voltage;
wherein in the sensing phase, the first control signal is at high voltage, the second control signal is at low voltage, and the third control signal is at low voltage;
wherein in the data write-in phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at high voltage; and
wherein the first control signal, the second control signal, and the third control signal of pixels of a current row and the first control signal, the second control signal, and the third control signal of pixels of an adjacent row are configured so that the data write-in phase of the pixels of the current row and the data write-in phase of the pixels of the adjacent row do not overlap, and the reset phase and the sensing phase of the pixels of the current row respectively overlap the reset phase and the sensing phase of the pixels of the adjacent row.

### Claim 9 (depends on 8)

The pixel internal compensation circuit as claimed in claim 8, wherein in the light-emitting phase, the first control signal is at low voltage, the second control signal is at low voltage, and the third control signal is at low voltage.