# US 10,504,426 B2 · System and method for external pixel compensation

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- Number: US 10,504,426 B2
- Document ID: US10504426B2
- Status: Granted
- Kind: B2
- Application number: 15/702,443
- Filed: 2017-09-12
- Published: 2018-03-22
- Granted: 2019-12-10
- Earliest claimed: 2016-09-23
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Jesse Aaron Richmond; Mohammad B. Vahid Far; Yafei Bi; Kingsuk Brahma
- Web page: https://patentgrep.com/patent/US10504426B2

## CPC

- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)}
- G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)}
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- H03F 3/265: {with field-effect transistors only}
- G09G 2300/0809: Several active elements per pixel in active matrix panels
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2320/0285: using tables for spatial correction of display data
- G09G 2320/0295: by monitoring each display pixel
- G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H03F: AMPLIFIERS

## Abstract

An electronic device includes a display panel. The display panel includes a plurality of pixels, each of which includes a driving thin-film-transistor (TFT) configured to receive driving data related to the operation of a respective pixel and a light-emitting diode configured to emit light based on the driving data provided to the TFT. The display panel also includes compensation circuitry configured to generate offset data from compressed offset data and apply the offset data to the pixel data to generate the driving data.

## Claims

### Claim 1

An electronic device, comprising:
a display panel, comprising:
a plurality of pixels, each pixel of the plurality of pixels comprising:
a driving thin-film-transistor (TFT) configured to receive driving data related to an operation of a respective pixel; and
a light-emitting diode configured to emit light based on the driving data provided to the TFT; and
compensation circuitry configured to generate offset data from compressed offset data and apply the offset data to pixel data to generate the driving data at least in part by transmitting the offset data for a period of time before transmitting the pixel data, wherein the compensation circuitry comprises:
a gamma digital-to-analog converter (DAC); and
an offset DAC, wherein the compensation circuitry is configured to provide compensated pixel data as the driving data by adding an output of the gamma DAC and the output of the offset DAC.

### Claim 2 (depends on 1)

The electronic device of claim 1, comprising a driver integrated circuit (IC) comprising the compensation circuitry.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the driver IC comprises a first input configured to receive the pixel data.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the driver IC comprises a second input configured to receive the compressed offset data, wherein the second input comprises a serial peripheral interface input.

### Claim 5 (depends on 4)

The electronic device of claim 4, wherein the driver IC comprises a memory coupled to the second input, wherein the memory is configured to store the compressed offset data.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the driver IC comprises a decoder coupled to the memory, wherein the decoder is configured to decompress the compressed offset data to generate the offset data.

### Claim 7 (depends on 2)

The electronic device of claim 2, wherein the driver IC is configured to receive the compressed offset data in parallel with the pixel data.

### Claim 8 (depends on 1)

The electronic device of claim 1, comprising a processing unit, wherein the processing unit is configured to provide the pixel data and the compressed offset data to the compensation circuitry along separate paths.

### Claim 9

A method, comprising:
receiving grey level pixel data;
converting the grey level pixel data via a gamma digital to analog converter (DAC) into converted pixel data;
converting offset data related non-uniformity between a plurality of pixels into converted offset data via an offset DAC;
applying the converted offset data to the converted pixel data in a summing circuit comprising a switched-capacitor circuit that receives the converted offset data to generate compensated driving data at least in part by closing a first switch of the switched-capacitor circuit to couple a capacitor of the switched-capacitor circuit to the offset DAC for a first time period; and
controlling emission of light from a light-emitting diode of a pixel of the plurality of pixels based on the compensated driving data.

### Claim 10 (depends on 9)

The method of claim 9, comprising applying the converted offset data to the converted pixel data by opening the first switch of the switched-capacitor circuit and closing a second switch of the switched-capacitor circuit to couple the capacitor of the switched-capacitor circuit to the gamma DAC.

### Claim 11 (depends on 10)

The method of claim 10, comprising applying the converted offset data to the converted pixel data by opening the first switch of the switched-capacitor circuit and closing the second switch of the switched-capacitor circuit for a second time period.

### Claim 12 (depends on 9)

The method of claim 9, wherein controlling the emission of light from the light-emitting diode comprises converting the compensated driving data to a driving voltage and supplying the driving voltage to a thin-film-transistor (TFT) associated with the light-emitting-diode.

### Claim 13 (depends on 9)

The method of claim 9, comprising receiving the grey level pixel data separately from the compressed offset data and decompressing the compressed offset data to generate the offset data.

### Claim 14

An electronic display, comprising:
compensation circuitry comprising:
a first input configured to receive pixel data related to generating an image on a display comprising a plurality of pixels;
a second input configured to receive, separate from receiving the pixel data, compressed offset data related to non-uniformity between the plurality of pixels;
a decoder configured to decompress the compressed offset data to generate offset data;
an offset digital-to-analog converter (DAC) coupled to the decoder and configured to convert the offset data into converted offset data;
a gamma DAC configured to convert the pixel data into converted pixel data; and
a summing circuit coupled to the offset DAC and the gamma DAC and configured to:
close a switch coupled between an input to the summing circuit and an output of the summing circuit; and
add, in response to the closing of the switch, the converted offset data to the converted pixel data to generate driving data to compensate for the non-uniformity between the plurality of pixels.

### Claim 15 (depends on 14)

The electronic display of claim 14, wherein the summing circuit comprises a capacitor coupled to a first switch and a second switch.

### Claim 16 (depends on 15)

The electronic display of claim 15, wherein the first switch is coupled to the offset DAC, wherein the first switch is configured to be toggled to selectively couple the capacitor to the offset DAC for a first time period.

### Claim 17 (depends on 16)

The electronic display of claim 16, wherein the second switch is coupled to the gamma DAC, wherein the second switch is configured to be toggled to selectively couple the capacitor to the gamma DAC for a second time period.
