# US 10,504,413 B2 · Display apparatus and method of driving the same

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- Number: US 10,504,413 B2
- Document ID: US10504413B2
- Status: Granted
- Kind: B2
- Application number: 15/804,988
- Filed: 2017-11-06
- Published: 2018-05-17
- Granted: 2019-12-10
- Earliest claimed: 2016-11-15
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Hyojin Lee; Jihye Kim; Jae-Hyeon Jeon
- Web page: https://patentgrep.com/patent/US10504413B2

## CPC

- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing
- G09G 2310/0202: Addressing of scan or signal lines
- G09G 2310/0218: with collection of electrodes in groups for n-dimensional addressing
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/021: Power management, e.g. power saving
- G09G 2330/023: using energy recovery or conservation
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display apparatus includes a display panel including a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the plurality of data lines including a plurality of first data lines and a plurality of second data lines, a scan driver configured to sequentially output a plurality of scan signals to the plurality of scan lines, a first data driver circuit configured to sequentially output a plurality of first data signals to the plurality of first data lines, and a second data driver circuit configured to sequentially output a plurality of second data signals to the plurality of second data lines based on a feedback signal received from the first data driver circuit.

## Claims

### Claim 1

A display apparatus comprising:
a display panel comprising a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines;
a scan driver configured to sequentially output a plurality of scan signals to the plurality of scan lines;
a first data driver circuit configured to sequentially output a plurality of first data signals to the plurality of first data lines; and
a second data driver circuit configured to sequentially output a plurality of second data signals to the plurality of second data lines based on a feedback signal received from the first data driver circuit; and
a timing controller,
wherein each of the first and second data driver circuits comprises a plurality of output channels, and the timing controller is configured to provide each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among the plurality of output channels, and
wherein the first data driver circuit is configured:
to generate a first internal clock signal based on an external clock signal,
to sequentially output a plurality of first data signals based on the first internal clock signal and the delay difference, and
to supply the second data driver circuit with the feedback signal corresponding to an output timing of a last first data signal from among the plurality of first data signals, the feedback signal being for generating a second internal clock signal used in the second data driver circuit.

### Claim 2 (depends on 1)

The display apparatus of claim 1, wherein the second data driver circuit is configured:
to generate the second internal clock signal delayed from an external clock signal based on the feedback signal,
to sequentially output a plurality of second data signals based on the second internal clock signal and the delay difference, and
to output the feedback signal corresponding to an output timing of a last second data signal from among the plurality of second data signals.

### Claim 3 (depends on 1)

The display apparatus of claim 1, wherein each of the first and second data driver circuits comprises:
a clock generator configured to generate an internal clock signal; and
a data processor configured to convert image data into a data signal that is an analog voltage.

### Claim 4 (depends on 1)

The display apparatus of claim 1, wherein a last output channel from among a plurality of output channels of the first data driver circuit is configured to output a data signal at an output timing that is the same as that of a first output channel from among a plurality of output channels of the second data driver circuit.

### Claim 5

A display apparatus comprising:
a display panel comprising a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the plurality of data lines comprising a plurality of first data lines and a plurality of second data lines;
a scan driver configured to sequentially output a plurality of scan signals to the plurality of scan lines;
a first data driver circuit configured to sequentially output a plurality of first data signals to the plurality of first data lines;
a second data driver circuit configured to sequentially output a plurality of second data signals to the plurality of second data lines based on a feedback signal received from the first data driver circuit; and
a timing controller,
wherein each of the first and second data driver circuits comprises a plurality of output channels, and the timing controller is configured to provide each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among the plurality of output channels, and
wherein the first data driver circuit is configured:
to generate a first internal clock signal based on an external clock signal,
to sequentially output a plurality of first data signals based on the first internal clock signal and the delay difference,
to generate a second internal clock signal delayed from the first internal clock signal based on the delay difference, and
to output the feedback signal as the second internal clock signal.

### Claim 6 (depends on 5)

The display apparatus of claim 5, wherein the second data driver circuit is configured:
to sequentially output a plurality of second data signals based on the second internal clock signal,
to generate a third internal clock signal delayed from the second internal clock signal based on the delay difference, and
to output the feedback signal as the third internal clock signal.

### Claim 7

A method of driving a display apparatus that comprises a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the method comprising:
outputting a scan signal to the plurality of scan lines;
sequentially outputting a plurality of first data signals to a plurality of first data lines by a first data driver circuit;
sequentially outputting a plurality of second data signals to a plurality of second data lines, based on a feedback signal received from the first data driver circuit, by a second data driver circuit, the plurality of second data signals being delayed from the plurality of first data signals;
supplying each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among a plurality of output channels, wherein each of the first and second data driver circuits comprises a plurality of output channels;
generating a first internal clock signal, by the first data driver circuit, based on an external clock signal;
sequentially outputting a plurality of first data signals based on the first internal clock signal and the delay difference; and
supplying, to the second data driver circuit, the feedback signal corresponding to an output timing of a last first data signal from among the plurality of first data signals, the feedback signal being for generating a second internal clock signal used in the second data driver circuit.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
generating the second internal clock signal, by the second data driver circuit, that is delayed from an external clock signal based on the feedback signal;
sequentially outputting a plurality of second data signals based on the second internal clock signal and the delay difference; and
outputting the feedback signal corresponding to an output timing of a last second data signal from among the plurality of second data signals.

### Claim 9 (depends on 7)

The method of claim 7, wherein a last output channel from among a plurality of output channels of the first data driver circuit is configured to output a data signal at an output timing that is the same as that of a first output channel from among a plurality of output channels of the second data driver circuit.

### Claim 10

A method of driving a display apparatus that comprises a plurality of data lines and a plurality of scan lines crossing the plurality of data lines, the method comprising:
outputting a scan signal to the plurality of scan lines;
sequentially outputting a plurality of first data signals to a plurality of first data lines by a first data driver circuit;
sequentially outputting a plurality of second data signals to a plurality of second data lines, based on a feedback signal received from the first data driver circuit, by a second data driver circuit, the plurality of second data signals being delayed from the plurality of first data signals;
supplying each of the first and second data driver circuits with a delay difference between output signals of a first output channel and a last output channel from among a plurality of output channels, wherein each of the first and second data driver circuits comprises a plurality of output channels;
generating a first internal clock signal, by the first data driver circuit, based on an external clock signal;
sequentially outputting a plurality of first data signals based on the first internal clock signal and the delay difference;
generating a second internal clock signal delayed from the first internal clock signal based on the delay difference; and
outputting the second internal clock signal as the feedback signal to the second data driver circuit.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
sequentially outputting a plurality of second data signals based on the second internal clock signal;
generating a third internal clock signal delayed from the second internal clock signal based on the delay difference; and
outputting the feedback signal as the third internal clock signal.