# US 10,504,411 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,411 B2 - Document ID: US10504411B2 - Status: Granted - Kind: B2 - Application number: 15/496,517 - Filed: 2017-04-25 - Published: 2017-10-26 - Granted: 2019-12-10 - Earliest claimed: 2016-04-26 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd - Inventors: Wontae Kim; Taegon Im - Web page: https://patentgrep.com/patent/US10504411B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 5/008: {Clock recovery} - G09G 2310/0218: with collection of electrodes in groups for n-dimensional addressing - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device according to an embodiment of the inventive concept includes a data driving unit, a gate driving unit, a signal control unit for controlling driving of the data driving unit and the gate driving unit, and a display panel. The data driving unit generates an internal clock signal for outputting data voltages corresponding to image data, and the display panel displays an image corresponding to the data voltages in response to a gate driving signal outputted from the gate driving unit. The data driving unit includes a filtering unit for converting a first frequency control signal received from the signal control unit so as to generate a second frequency control signal, and a clock training unit for training a clock signal received from the signal control unit so as to generate the internal clock signal in response to the second frequency control signal. ## Claims ### Claim 1 A display device comprising: a signal control unit configured to output a gate driving signal, a clock signal including frequency information, a plurality of image data corresponding to a plurality of frame images, and a first frequency control signal for defining a plurality of frame periods in which the plurality of frame images are respectively displayed; a data driving unit including: a signal processing unit configured to train the clock signal received from the signal control unit to generate an internal clock signal, and a data converting unit configured to convert the plurality of image data to a plurality of data voltages in response to the internal clock signal, and to output the data voltages; a gate driving unit configured to output a gate signal in response to the gate driving signal received from the signal control unit; and a display panel configured to display the plurality of frame images corresponding respectively to the plurality of data voltages in response to the gate signal, wherein the signal processing unit includes: a filtering unit configured to receive the first frequency control signal, and generate a second frequency control signal having a first level when a level of the first frequency control signal is maintained at the first level for a preset determination period, and having a second level when a level of the first frequency control signal is maintained at the second level for the determination period; and a clock training unit configured to perform clock training for generating the internal clock signal in response to the second frequency control signal. ### Claim 2 (depends on 1) The display device of claim 1, wherein the data driving unit further comprises a reference clock signal generating unit configured to generate a reference clock signal for determining the determination period, and the filtering unit compares a level of the first frequency control signal for each cycle of the reference clock signal, and, when the first frequency control signal has been maintained at one level of the first and second levels for at least n cycles of the reference clock signal, where n is a natural number greater than or equal to two, the filtering unit converts a level of the second frequency control signal to the one level of the first frequency control signal from an (n+1)-th cycle of the reference clock signal. ### Claim 3 (depends on 2) The display device of claim 2, wherein, when a level of the first frequency control signal is not maintained to be constant at one level of the first and second levels for the n cycles, the filtering unit maintains a level of the second frequency control signal to be unconverted in the (n+1)-th cycle. ### Claim 4 (depends on 2) The display device of claim 2, wherein the filtering unit comprises: a signal generating unit configured to output n input signals respectively including level information of the first frequency control signal in the n cycles; a comparing unit configured to compare the n input signals to determine whether a level of the first frequency control signal remains constant for the n cycles; and an output unit configured to output, when the comparing unit determines that the level of the first frequency control signal has remained constant for the n cycles, the second frequency control signal having, in the (n+1)-th cycle, the same level as the level of the first frequency control signal. ### Claim 5 (depends on 4) The display device of claim 4, wherein the signal generating unit comprises n flip-flops configured to generate the n input signals, and n inverted signals respectively having level values inverted from level values of the n input signals. ### Claim 6 (depends on 5) The display device of claim 5, wherein the comparing unit comprises: a first NAND circuit configured to combine the n input signals to output a first comparison signal; a second NAND circuit configured to combine the n inverted signals to output a second comparison signal; and a latch unit connected to each of the first NAND circuit and the second NAND circuit, and configured to output a result signal having one of the first level and the second level on the basis of the first comparison signal and the second comparison signal. ### Claim 7 (depends on 6) The display device of claim 6, wherein the output unit comprises: a first inverter configured to output an inverted result signal having a level inverted from a level of the result signal; a second inverter configured to invert the inverted result signal to the result signal again; and an output flip-flop configured to convert, in the (n+1)-th cycle, a level of the second frequency control signal to the level of the result signal. ### Claim 8 (depends on 1) The display device of claim 1, wherein the signal control unit further outputs a plurality of blank data, the plurality of image data are outputted in the plurality of frame periods, and the plurality of blank data are outputted in a plurality of blank periods alternately repeated with the plurality of frame periods respectively. ### Claim 9 (depends on 8) The display device of claim 8, wherein each of the plurality of blank data comprises pattern data for the clock training, and the clock training unit performs the clock training using the pattern data. ### Claim 10 (depends on 8) The display device of claim 8, wherein each of the plurality of image data comprises dummy data and active data, one frame period of the plurality of frame periods is disposed between a first blank period and a second blank period, and a dummy data period included in the one frame period is disposed to be adjacent to at least one of the first blank period or the second blank period. ### Claim 11 A data driving unit comprising: a filtering unit configured to receive a first frequency control signal from a signal control unit, and to generate, on the basis that a level of the first frequency control signal is maintained to be constant at one level of a first level and a second level for a preset determination period, a second frequency control signal converted to have the same level as the one level; a clock training unit configured to receive a clock signal including frequency information from the signal control unit, and to generate an internal clock signal corresponding to the clock signal while performing training of the clock signal in response to the second frequency control signal; and a data converting unit configured to convert a plurality of image data corresponding to a plurality of frame images to a plurality of data voltages in response to the internal clock signal, and to output the data voltages. ### Claim 12 (depends on 11) The data driving unit of claim 11, further comprising a reference clock signal generating unit configured to generate a reference clock signal for determining the determination period, wherein the filtering unit compares a level of the first frequency control signal for each cycle of the reference clock signal, and, when the first frequency control signal has been maintained at one level of the first and second levels for at least n cycles of the reference clock signal, where n is a natural number greater than or equal to two, the filtering unit converts a level of the second frequency control signal to the one level of the first frequency control signal from an (n+1)-th cycle of the reference clock signal. ### Claim 13 (depends on 12) The data driving unit of claim 12, wherein, when a level of the first frequency control signal is not maintained to be constant at one level of the first and second levels for the n cycles, the filtering unit maintains a level of the second frequency control signal to be unconverted in the (n+1)-th cycle. ### Claim 14 (depends on 12) The data driving unit of claim 12, wherein the filtering unit comprises: a signal generating unit configured to output n input signals respectively including level information of the first frequency control signal in the n cycles; a comparing unit configured to compare the n input signals to determine whether a level of the first frequency control signal remains constant for the n cycles; and an output unit configured to output, when the comparing unit determines that the level of the first frequency control signal has remained constant for the n cycles, the second frequency control signal having, in the (n+1)-th cycle, the same level as the level of the first frequency control signal. ### Claim 15 (depends on 14) The data driving unit of claim 14, wherein the signal generating unit comprises n flip-flops configured to generate the n input signals, and n inverted signals respectively having level values inverted from level values of the n input signals. ### Claim 16 (depends on 15) The data driving unit of claim 15, wherein the comparing unit comprises: a first NAND circuit configured to combine the n input signals to output a first comparison signal; a second NAND circuit configured to combine the n inverted signals to output a second comparison signal; and a latch unit connected to each of the first NAND circuit and the second NAND circuit, and configured to output a result signal having one of the first level and the second level on the basis of the first comparison signal and the second comparison signal. ### Claim 17 (depends on 14) The data driving unit of claim 14, wherein the output unit comprises: a first inverter configured to output an inverted result signal having a level inverted from a level of the result signal; a second inverter configured to invert the inverted result signal to the result signal again; and an output flip-flop configured to convert, in the (n+1)-th cycle, a level of the second frequency control signal to the level of the result signal. ### Claim 18 A method of driving a display device comprising: outputting a clock signal including frequency information, a gate driving signal, a plurality of image data corresponding to a plurality of frame images, and a first frequency control signal for defining a plurality of frame periods in which the plurality of frame images are respectively displayed; generating a second frequency control signal having a first level when a level of the first frequency control signal is maintained at the first level for a preset determination period, and having a second level when a level of the first frequency control signal is maintained at the second level for the determination period; generating an internal clock signal while performing training of the clock signal in response to the second frequency control signal; converting the plurality of image data to a plurality of data voltages in response to the internal clock signal and outputting the data voltages, and outputting a gate signal in response to the gate driving signal; and displaying the plurality of frame images corresponding respectively to the plurality of data voltages in response to the gate signal. ### Claim 19 (depends on 18) The method of driving a display device of claim 18, wherein the generating of the second frequency control signal comprises: generating a reference clock signal for determining the determination period; and comparing a level of the first frequency control signal for each cycle of the reference clock signal, and, when the first frequency control signal has been maintained at one level of the first and second levels for at least n cycles of the reference clock signal, where n is a natural number greater than or equal to two, converting a level of the second frequency control signal to the one level of the first frequency control signal from an (n+1)-th cycle of the reference clock signal. ### Claim 20 (depends on 19) The method of driving a display device of claim 19, wherein, when a level of the first frequency control signal is not maintained to be constant at one level of the first and second levels for the n cycles, a level of the second frequency control signal is maintained to be unconverted in the (n+1)-th cycle.