# US 10,504,407 B2 · Display panel with slim border and method of driving display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,407 B2 - Document ID: US10504407B2 - Status: Granted - Kind: B2 - Application number: 15/232,790 - Filed: 2016-08-09 - Published: 2017-03-02 - Granted: 2019-12-10 - Earliest claimed: 2015-08-28 - Assignees: Au Optronics Corporation - Applicants: AU Optronics Corp. - Inventors: Shuo-Wen Jang; Jui-Chi Lo - Web page: https://patentgrep.com/patent/US10504407B2 ## CPC - G09G 3/2085: {Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination} - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0205: Simultaneous scanning of several lines in flat panels - G09G 2310/0221: with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display panel includes a pixel block, a data circuit, and a data source. The pixel block includes a first sub-pixel coupled to a first data line, and N second sub-pixels. Each second sub-pixel of the N second sub-pixels is coupled to a corresponding second data line of N second data lines. The data circuit includes N switches. Each switch of the N switches is coupled to a corresponding second sub-pixel. When N voltage levels are sequentially outputted from the data source to the first data line and the N second data lines, the N switches are disabled sequentially. ## Claims ### Claim 1 A display panel, comprising: a pixel block, comprising: a first sub-pixel coupled to a first data line; and N second sub-pixels, each second sub-pixel of the N second sub-pixels coupled to a corresponding second data line of N second data lines; a data circuit, comprising: N switches, each switch of the N switches coupled to a corresponding second data line for reaching a corresponding second sub-pixel, wherein N is a positive integer; and a data source coupled to the first data line and the N switches; wherein N voltage levels are outputted from the data source to the first sub-pixel via the first data line; and wherein each of the N switches is enabled in sequence for forwarding a corresponding one of N voltage levels to the corresponding second sub-pixel via the corresponding second data line; wherein each of N voltage levels passes through the first sub-pixel before reaching each of N switches. ### Claim 2 (depends on 1) The display panel of claim 1, wherein when the N voltage levels are sequentially outputted from the data source to the first data line and the N second data lines, the N switches are enabled and then disabled sequentially. ### Claim 3 (depends on 1) The display panel of claim 1, wherein two data circuits respectively coupled to two adjoining pixel blocks are disposed to different sides of the two adjoining pixel blocks. ### Claim 4 (depends on 1) The display panel of claim 1, wherein the N second sub-pixels and the first sub-pixel are allocated sequentially according to a pixel sequence formed by a red sub-pixel, a green sub-pixel, and a blue sub-pixel. ### Claim 5 (depends on 1) The display panel of claim 1, further comprising: a gate circuit for driving a plurality of sub-pixels of at least one pixel block; wherein the gate circuit and the data circuit are disposed to two opposite sides of the pixel block. ### Claim 6 (depends on 1) The display panel of claim 1, wherein widths of a plurality of pixel blocks of the display panel are identical. ### Claim 7 (depends on 1) The display panel of claim 1, wherein a width of the data circuit is smaller than or equal to a width of the pixel block. ### Claim 8 (depends on 1) The display panel of claim 1, wherein a width of the data circuit is 1-2 times greater than a width of the pixel block. ### Claim 9 (depends on 1) The display panel of claim 1, wherein widths of a plurality of pixel blocks of the display panel are not all the same. ### Claim 10 (depends on 1) The display panel of claim 1, wherein the data circuit is a demultiplexer. ### Claim 11 (depends on 1) The display panel of claim 1, wherein the first sub-pixel is blue. ### Claim 12 (depends on 1) The display panel of claim 1, further comprising: a gate circuit for driving a plurality of sub-pixels of at least one pixel block; and a fan-out circuit, wherein the fan-out circuit is disposed between the data circuit and the gate circuit; wherein the plurality of sub-pixels form a display area, the data circuit is disposed adjacent to a perimeter of the display area, and the gate circuit is further away from the perimeter of the display area. ### Claim 13 (depends on 1) The display panel of claim 1, wherein the first data line connects the data source to each of N switches. ### Claim 14 (depends on 1) The display panel of claim 1, wherein the data circuit is a demultiplexer. ### Claim 15 A display panel, comprising: a pixel block, comprising: a first sub-pixel coupled to a first data line; and N second sub-pixels, each second sub-pixel of the N second sub-pixels coupled to a corresponding second data line of N second data lines; a data circuit, comprising: N switches, each switch of the N switches coupled to a corresponding second data line for reaching a corresponding second sub-pixel; and a data source coupled to the first data line and the N switches; wherein N voltage levels are outputted from the data source to the first sub-pixel via the first data line, each of the N switches is enabled initially, and each of the N switches is disabled in sequence after forwarding a corresponding one of N voltage levels to the first data line and N data line, and N is a positive integer; wherein each of N voltage levels passes through the first sub-pixel before reaching each of N switches. ### Claim 16 (depends on 15) The display panel of claim 15, wherein two data circuits respectively coupled to two adjoining pixel blocks are disposed to different sides of the two adjoining pixel blocks. ### Claim 17 (depends on 15) The display panel of claim 15, wherein the N second sub-pixels and the first sub-pixel are allocated sequentially according to a pixel sequence formed by a red sub-pixel, a green sub-pixel, and a blue sub-pixel. ### Claim 18 (depends on 15) The display panel of claim 15, wherein widths of a plurality of pixel blocks of the display panel are identical. ### Claim 19 (depends on 15) The display panel of claim 15, wherein a width of the data circuit is smaller than or equal to a width of the pixel block.