# US 10,504,401 B2 · Display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,504,401 B2 - Document ID: US10504401B2 - Status: Granted - Kind: B2 - Application number: 16/029,652 - Filed: 2018-07-09 - Published: 2019-06-20 - Granted: 2019-12-10 - Earliest claimed: 2017-12-18 - Assignees: Au Optronics Corporation - Applicants: Au Optronics Corporation - Inventors: Wei-Chu Hsu; Ko-Ruey Jen - Web page: https://patentgrep.com/patent/US10504401B2 ## CPC - G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)} - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 2300/0804: Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling - G09G 2320/0242: Compensation of deficiencies in the appearance of colours - G09G 2320/0666: for control of colour parameters, e.g. colour temperature - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display panel is provided. A pixel array includes a plurality of first subpixels, a first source line coupled to the first subpixels, a plurality of second subpixels displaying the same with the first subpixels, and a second source line coupled to the second subpixels. A multiplexer circuit includes a first switch coupled between the first source line and a source driver and a second switch coupled between the second source line and the source driver. A first compensation capacitor couples between the first source line and a reference voltage, and a capacitance value thereof is related to a cut-off time point of the first switch. A second compensation capacitor couples between the second source line and the reference voltage, and a capacitance value thereof the second compensation capacitor is related to a cut-off time point of the second switch different from the cut-off time point of the second switch. ## Claims ### Claim 1 A display panel, comprising: a pixel array, comprising: a plurality of first subpixels; a first source line, coupled to the first subpixels; a plurality of second subpixels, displaying a same color light as the first subpixels; and a second source line, coupled to the second subpixels; a multiplexer circuit, comprising: a first switch, coupled between the first source line and a source driver; and a second switch, coupled between the second source line and the source driver; a first compensation capacitor, coupled between the first source line and a reference voltage, wherein a capacitance value of the first compensation capacitor is related to a cut-off time point of the first switch; and a second compensation capacitor, coupled between the second source line and the reference voltage, wherein a capacitance value of the second compensation capacitor is related to a cut-off time point of the second switch, wherein the cut-off time point of the first switch is different from the cut-off time point of the second switch. ### Claim 2 (depends on 1) The display panel as claimed in claim 1, wherein the first switch and the second switch are turned on in sequence in a horizontal scan period. ### Claim 3 (depends on 2) The display panel as claimed in claim 2, wherein in the horizontal scan period, the cut-off time point of the first switch is prior to the cut-off time point of the second switch, and the capacitance value of the first compensation capacitor is less than the capacitance value of the second compensation capacitor. ### Claim 4 (depends on 3) The display panel as claimed in claim 3, wherein a first compensation time for the first subpixels by the first source line is greater than a second compensation time for the second subpixels by the second source line such that the capacitance value of the first compensation capacitor is less than the capacitance value of the second compensation capacitor. ### Claim 5 (depends on 4) The display panel as claimed in claim 4, wherein the first compensation time ranges between the cut-off time point of the first switch and a cut-off time point of the horizontal scan period, and the second compensation time ranges between the cut-off time point of the second switch and the cut-off time point of the horizontal scan period. ### Claim 6 (depends on 1) The display panel as claimed in claim 1, wherein the first switch is coupled to a first terminal of the first source line, the first compensation capacitor is coupled to a second terminal of the first source line, the second switch is coupled to a first terminal of the second source line, and the second compensation capacitor is coupled to a second terminal of the second source line. ### Claim 7 (depends on 1) The display panel as claimed in claim 1, wherein each of the first subpixels and the second subpixels comprises: a first transistor, having a source terminal coupled to a first voltage, a gate terminal, and a drain terminal; a first capacitor, coupled between a second voltage and the gate terminal of the first transistor; a second transistor, having a source terminal coupled to the drain terminal of the first transistor, a gate terminal receiving a scan signal, and a drain terminal coupled to the gate terminal of the first transistor; a third transistor, having a source terminal coupled to the drain terminal of the first transistor, a gate terminal receiving a light emitting signal, and a drain terminal; and an organic light emitting diode, coupled between the drain terminal of the third transistor and a common voltage; wherein one of the first voltage and the second voltage is a data voltage transmitted by the first source line or the second source line, and the other one of the first voltage and the second voltage is a system voltage different from the common voltage. ### Claim 8 (depends on 1) The display panel as claimed in claim 1, wherein the reference voltage is a common voltage. ### Claim 9 (depends on 1) The display panel as claimed in claim 1, wherein the source driver is disposed on a circuit board coupled to the display panel.