# US 10,503,854 B1 · Method and system for generating validation tests > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,854 B1 - Document ID: US10503854B1 - Status: Granted - Kind: B1 - Application number: 15/725,307 - Filed: 2017-10-05 - Granted: 2019-12-10 - Earliest claimed: 2017-10-05 - Assignees: Cadence Design Systems, Inc. - Applicants: Cadence Design Systems, Inc. - Inventors: Meir Ovadia - Web page: https://patentgrep.com/patent/US10503854B1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G01R 31/2803: {by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor (testing electronic digital computers G06F11/00)} - G01R 31/317: Testing of digital circuits - G01R 31/3181: Functional testing (G01R31/3177 takes precedence) - G06F 11/3672: {Test management} - G06F 30/30: Circuit design - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/3308: using simulation - G01R 31/2848: {using simulation} - G06F 11/07: Responding to the occurrence of a fault, e.g. fault tolerance - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F 11/26: Functional testing - G06F 11/36: Prevention of errors by analysis, debugging or testing of software - G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) - G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A method for generating a validation test, may include obtaining, using a processor, a validated scenario for generating a test for a verification model, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph. The method may also include analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with a faulty scheduler of a verification model to be tested. The method may further include, upon identifying the identified action, amending, using the processor, the verified scenario by removing the identified action from the graph. ## Claims ### Claim 1 A method for amending a validated scenario for generating a validation test, the method comprising: obtaining, using a processor, the validated scenario for generating a test for a design under test having a faulty component, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph; analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with the faulty component of the design under test; and upon identifying the identified action, using the processor, amending the validated scenario by removing the identified action from the graph to provide an amended validated scenario. ### Claim 2 (depends on 1) The method of claim 1, further comprising, using the processor, generating a test using the amended validated scenario. ### Claim 3 (depends on 1) The method of claim 1, further comprising, using the processor, determining whether the identified action was in between two actions along a topological order, and if so, connecting the two actions in the graph by a directed edge. ### Claim 4 (depends on 1) The method of claim 1, further comprising, using the processor, determining whether the identified action was a first action or a last action on the graph, and if so, replacing the removed identified action by a fiction action. ### Claim 5 (depends on 1) The method of claim 1, further comprising, using the processor, determining whether the identified action produces a resource which is later used by an action of said plurality of actions on the graph, and if so, discarding the validated scenario. ### Claim 6 (depends on 1) The method of claim 1, further comprising receiving information on the faulty component. ### Claim 7 A non-transitory computer readable storage medium for amending a validated scenario for generating a validation test, having stored thereon instructions that when executed by a processor will cause the processor to: obtain, using a processor, the validated scenario for generating a test for a design under test having a faulty component, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph; analyze, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with the faulty component of the design under test; and upon identifying the identified action, amend, using the processor the validated scenario by removing the identified action from the graph to provide an amended validated scenario. ### Claim 8 (depends on 7) The non-transitory computer readable storage medium of claim 7, wherein the instructions stored thereon when executed by a processor will further cause the processor to generate a test using the amended validated scenario. ### Claim 9 (depends on 7) The non-transitory computer readable storage medium of claim 7, wherein the instructions stored thereon when executed by a processor will further cause the processor to determine whether the identified action was in between two actions along a topological order, and if so, connect the two actions in the graph by a directed edge. ### Claim 10 (depends on 7) The non-transitory computer readable storage medium of claim 7, wherein the instructions stored thereon when executed by a processor will further cause the processor to determine whether the identified action was a first action or a last action on the graph, and if so, replace the removed identified action by a fiction action. ### Claim 11 (depends on 7) The non-transitory computer readable storage medium of claim 7, wherein the instructions stored thereon when executed by a processor will further cause the processor to determine whether the identified action produces a resource which is later used by an action of said plurality of actions on the graph, and if so, discarding the validated scenario. ### Claim 12 (depends on 7) The non-transitory computer readable storage medium of claim 7, wherein the instructions stored thereon when executed by a processor will further cause the processor to receive information on the faulty component. ### Claim 13 A system for amending a validated scenario for generating a validation test, the system comprising: a memory and a processor configured to: obtain, using a processor, the validated scenario for generating a test for a design under test having a faulty component, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph; analyze, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with the faulty component of the design under test; and upon identifying the identified action, amend, using the processor the validated scenario by removing the identified action from the graph to provide an amended validated scenario. ### Claim 14 (depends on 13) The system of claim 13, wherein the processor is configured to generate a test using the amended validated scenario. ### Claim 15 (depends on 13) The system of claim 13, wherein the processor is configured to determine whether the identified action was in between two actions along a topological order, and if so, connect the two actions in the graph by a directed edge. ### Claim 16 (depends on 13) The system of claim 13, wherein the processor is configured to determine whether the identified action was a first action or a last action on the graph, and if so, replace the removed identified action by a fiction action. ### Claim 17 (depends on 13) The system of claim 13, wherein the processor is configured to determine whether the identified action produces a resource which is later used by an action of said plurality of actions on the graph, and if so, discarding the validated scenario. ### Claim 18 (depends on 13) The system of claim 13, wherein the processor is configured to receive information on the faulty component. ### Claim 19 (depends on 18) The system of claim 18, further comprising an input device for receiving the information.